Power Integrations, Inc.

Other

Vladimir Rumennik

Donald Ray Disney

Janardhanan S Ajit

Wayne Bryan Grabowski

Robert W Busse

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

High-voltage transistor with multi-layer conduction region

Method of making a high-voltage transistor with buried conduction regions

A MOSFET that provides high current conduction at high frequency includes a deposited layer over a substrate of a first conductivity type, with source and drain regions adjoining a top surface of the epitaxial layer. The drain region has a first portion that extends vertically through the epitaxial layer to connect to the substrate and a second portion that extends laterally along the top surface. A first region is disposed in the epitaxial layer between the extended region and the source region. An insulated gate is located above the first region between the source region and the second portion of the drain region. A drain metal layer contacts a bottom surface of the substrate, and a source metal layer that substantially covers the top surface connect to the source region.

High current field-effect transistor

A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.

Method of making a high-voltage transistor with multiple lateral conduction layers

A trench MOSFET that includes a charge carrier getter region to substantially deplete a plurality of body regions during an off-state of this MOSFET to produce a very low off-state leakage current. In a first class of embodiments, this charge carrier getter region is a thin layer of material, of opposite conductivity type to that of the body regions, and located between a plurality of gate regions and the body regions. In a second class of embodiments, the gate regions are of opposite conductivity type to the body regions to function as a charge carrier getter region as well as a gate region.

Bi-directional power trench MOS field effect transistor having low

In a method for constructing a semiconducting device, within a substrate of a first conductivity type there is formed a well of second conductivity type. Within the well, an extended drain region of a first conductivity type is formed. An insulating region over the extended drain region is formed. A gate region is formed on a surface of the substrate. A first side of the gate region is adjacent to a first end of the extended drain region. A drain region of the first conductivity type is formed. The drain region is in contact with a second end of the extended drain region. A source region is formed on a second side of the gate region.

Method of making high voltage transistor

A bi-directional switch includes a well region of a first conductivity type placed within a substrate. A first region of second conductivity type is placed within the well. A second contact region of second conductivity type is placed within the well. A drift region of second conductivity is placed between the first contact and the second contact. The drift region is separated from the first contact by a first channel region and is separated from the second contact by a second channel region. A first gate region is placed over the first channel region and a second gate region over the second channel region.

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Los Altos, CA, United States of America

Vladimir Rumennik