International Business Machines Corporation

Vladimir Riso

Rene J Glaise

Christian A Jacquart

Raymond J Wilfinger

Roland E Kuhne

James F Dubil

Howard N Leighton

Alain Dauby

Alain M Falcoz

Daniel Roger-Rodes

A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines. The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7. The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.

Bus interface device for a data processing system

This specification describes a charge-transfer device transversal filter chip in which an input signal is fed in parallel into a number of channels the outputs of which are summed together to provide the desired transversal filter transfer function. Each channel contains an analog shift register, a signal splitter and a polarity selector. The shift registers are of unequal length to provide a different delay thru each channel. The signal splitter provides a plurality of signal paths thru each channel while the polarity selector determines whether a given path in a given channel is added or subtracted in the summation to determine the gain of the given channel in the summation.

Universal transversal filter chip

High speed digital multiply-by-three device comprising a sum generation unit associated with a carry look-ahead unit, the latter comprising means for generating the carry bit C.sub.k.sub.+1 to be fed to the (k+1).sup.th stage of said sum generation unit by performing the logic function

High-speed digital multiply-by-device

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Nice, France

Vladimir Riso