Intel Corporation

Vladimir Penkovski

Jayesh Iyer

Boris A Babayan

Sergey Y Shishlov

Alexander V Butuzov

Nikolay Kosarev

Andrey Kluchnikov

Alexey Sivtsov

Candice Huang, Legal Representative

Sergey V Bulenkov

A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence.

Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor

A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.

Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor

A system for managing threads to handle transaction requests connected to input/output (I/O) subsystems to enable notification to threads to complete operations.

Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives

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Folsom, CA, United States of America

Vladimir Penkovski