Freescale Semiconductor,inc.

Nxp USA, Inc.

Infineon Technologies Ag

Synopsys, Inc.

Freescale Seimconductor, Inc.

Vladimir Litovtchenko

Florian Bogenberger

Dirk Moeller

Michael Rohleder

Thomas Henry Luedeke

Thomas Koch

Harald Luepken

Christoph Patzelt

Joachim Fader

Markus Regner

Oleksandr Sakada

Shivakumar Shankar Chonnad

Avni Bildhaiya

Longli Yu

Josef Maria Joachim Kruecken

Abdoul Aziz Kane

Radu Horia Iacob

A method for dependent failure analysis of a circuit design includes obtaining a circuit design comprising a plurality of circuit elements, and generating a first cone of influence and a second cone of influence for the circuit design. The first cone of influence corresponds to a first one or more inputs of the circuit design. The second cone of influence corresponds to a second one or more inputs of the circuit design. The method further includes determining a first shared circuit element of the circuit elements within a first intersection between the first cone of influence and the second cone of influence. Further, the method includes determining a first coupling factor based on the first intersection between the first cone of influence and the second cone of influence, and outputting the first shared circuit element and the first coupling factor to a memory.

Detecting shared rescources and coupling factors

A method for processing alarm signals is disclosed in which a multiplicity of selected alarm signals are first compared with a predefined alarm pattern. The multiplicity of the selected alarm signals are determined from the alarm signals. At least one response signal is then transmitted if the selected alarm signals match the predefined alarm pattern.

Method and apparatus for processing alarm signals

In various embodiments, an alarm handling circuitry is provided. The alarm handling circuitry may include a first alarm processing circuit configured to process a first received alarm and to provide a first processed alarm response signal, a second alarm processing circuit configured to process a second received alarm and to provide a second processed alarm response signal, and an interface between the first alarm processing circuit and the second alarm processing circuit configured to input an alive indication signal from the first alarm processing circuit to the second alarm processing circuit indicating whether the first alarm processing circuit is operating.

Alarm handling circuitry and method of handling an alarm

An electronic device has terminals for interfacing internal signals to other electronic devices. Each terminal is electrically coupled to a terminal driver and a terminal control circuit for receiving a terminal configuration defining the properties and multiplexing of the terminal. The actual configuration of the terminal driver is set according to the terminal configuration. The device has at least one terminal checker arranged for comparing the actual configuration to at least one check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed, and for, when said comparing indicates a not allowed configuration, setting the actual configuration to a default configuration. Advantageously safe operation of the device in a system is achieved by monitoring the configuration of the multiplexed terminals, and switching to a default configuration when in error.

Electronic device having multiplexed input/output terminals

A configuration controller for and a method of controlling a configuration of a circuitry are provided. The configuration controller comprises an input, a selection checker, a data selector and an output. The input receives an input configuration selection signal which is encoded according to a specific encoding scheme. The selection checker checks a correctness of the received input configuration selection signal and provides to the data selector a selection signal which indicates a specific configuration selection if the input configuration selection data is correct or indicates a default configuration selection if the input configuration selection signal is incorrect according to the specific encoding scheme. The data selector selects configuration data from its internal configuration data storage in accordance with the selection signal and provides the selected configuration data to the output.

Configuration controller for and a method of controlling a configuration of a circuitry

A microcontroller unit having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.

Microcontroller unit and method of operating a microcontroller unit

A processing apparatus, comprising at least a first processing unit and a second processing unit, is proposed. The first processing unit comprises a set of first stateful elements, the second processing unit comprises a set of second stateful elements. A set of synchronization data lines may connect the first stateful elements to the second stateful elements in a pairwise manner. A control unit may control the first processing unit, the second processing unit and the synchronization data lines so as to copy the states of the first stateful elements in parallel via the synchronization data lines to the second stateful elements in response to a synchronization request. A method of synchronizing the processing units is also proposed.

Processing apparatus and method of synchronizing a first processing unit and a second processing unit

A receive buffer of the type that receives information at regular time slots and is required to indicate any status changes to a micro control unit (MCU), the receive buffer including: a slot status field for storing slot status information at each timeslot for the receive buffer; a receive interrupt flag for sending a signal to the MCU for indicating a change of the slot status field on receipt of the information at each timeslot; characterized in that the receive buffer also includes: an empty slot recognition bit for determining if an empty slot is received and generating an indicator thereof, wherein the indicator is passed to the MCU instead of the useless empty slot status field.

Relating buffer management

An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request. The control logic unit may be arranged to determine whether the received request belongs to the current state of the processor, to grant the request when the received request does belong to the current state and to reject the request in case the request does not belong to the current state. The control logic unit may further include a control logic output for outputting an request grant signal when the request is granted.

Request controller, processing unit, arrangement, method for controlling requests and computer program product

In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Clock glitch detection circuit

A device receives a request for an amount of a resource. It determines for each resource provider in a set of resource providers a current load, a requested load corresponding to the requested amount of the resource, and an additional load corresponding to an expected state of an application. It determines for each of the resource providers an expected total load on the basis of the current load, the requested load, and the additional load. It subsequently selects from the set of resource providers a preferred resource provider on the basis of the expected total loads. The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device.

Resource allocation within multiple resource providers based on the incoming resource request and the expected state transition of the resource requesting application, and selecting a resource provider based on the sum of the percentage of the resource provider currently used, the requesting load as a percentage of the resource provider's total resource, and the additional load imposed by the expected state of the requesting application as a percentage of the resource provider's total resource

A data processing control unit for controlling two or more data processing operations SMI,SMI. The data processing control unit may include a control memory in control data may be stored which represents information about access to a main memory by the two or more data processing operations. A control data controller may be connected to the control memory. The control data controller may include a control data controller input or receiving an access request from one or more of the data processing operations. The control data controller may modify the data in the control memory upon receiving the access request. A process controller may be connected to the control memory. The process controller may control at least a part of the data processing operations SMI.SMIbased on a comparison of data in the control memory with a criterion. The process controller may include a process controller input for receiving the access request; and a process controller output for outputting a process control signal based on the comparison.

Data processing control unit for controlling multiple data processing operations

A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current an operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit. The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value. The comparator includes a comparator output for outputting a request grant signal when the comparison satisfies a predetermined grant criterion and outputting a request reject value when the comparison meets a predetermined reject criterion. A data controller is connected to the resource budget memory and the comparator output, for adjusting the budget value when the request grant signal is outputted.

Request controller, processing unit, method for controlling requests and computer program product

A method of grouping interrupts from a time-dependent data storage means in accordance with the types of the interrupts, the method comprising the steps of providing each part of the data storage means with an indicator of an event associated with the part, generating interrupts upon the occurrence of events in different parts of the data storage means, allocating interrupts associated with substantially the same part of the data storage means to a same processing means.

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Ebersberg, Germany

Vladimir Litovtchenko