Motorola Corporation

Analog Value Ltd.

Apple Inc.

Pixim Israel Ltd

Advasense Technologies Ltd.

Advasense Technologies (2004) Ltd.

Advasense Technologics (2004) Ltd.

Vladimir Koifman

Yachin Afek

Tiberiu Galambos

Israel Kashat

Anatoli Mordakhay

Michael Zarubinsky

Eliezer Sand

Ronen Paz

Natan Baron

Sergio Liberman

Kiyoshi Kase

Oded Norman

Yoram Salant

Eytan Engel

Joseph Shor

Noam Eshel

Zeituni Golan

Chen Bankirer

Vadim Tkachev

Tiberlu Galambos

Itai Mar-Or

Eyal Salomon

Dmitry Pudnik

An image sensor includes a logic die, including column readout circuits and bitlines connected to the column readout circuits. A sensor die is overlaid on the logic die. The image sensor includes an array of detector elements, each including a sensing circuit on the sensor die, which includes a photodiode, a floating diffusion node connected to one of the terminals of the photodiode, a reset transistor coupled to the floating diffusion node, and a source follower transistor. In each detector element, a pixel circuit on the logic die includes a select transistor, which has an input coupled to the output of the source follower and an output coupled to one of the bitlines. A current memory circuit is coupled to the input of the select transistor and is configured to sense and output a signal indicative of a level of noise in the detector element.

Image sensor with stacked pixels having high dynamic range and low noise

An image sensor includes a logic die, including column readout circuits, and a sensor die, overlaid on the logic die and including bitlines connected to the column readout circuits and an array of detector elements. Each detector element includes a photodiode having cathode and anode terminals and a floating diffusion node connected to one of the terminals of the photodiode. A first reset transistor is coupled between the floating diffusion node and a reset voltage. A source follower transistor has an input connected to the floating diffusion node and an output connect to a first terminal of an output capacitor having first and second terminals, with the first terminal. A second reset transistor is coupled between a second terminal of the output capacitor and the reset voltage. A select transistor is coupled between the second terminal of the output capacitor and one of the bitlines.

Image sensor with high dynamic range and low noise

An image sensor includes a logic die, including column readout circuits and bitlines connected to the column readout circuits. A sensor die is overlaid on the logic die. The image sensor includes an array of detector elements, each including a sensing circuit on the sensor die, which includes a photodiode, a floating diffusion nodea charge sharing transistor coupled between the photodiode and the floating diffusion node, a reset transistor coupled to the floating diffusion node, and a source follower transistor. In each detector element, a pixel circuit on the logic die includes a select transistor, which has an input coupled to the output of the source follower and an output coupled to one of the bitlines. Two current memory circuits are coupled to the input of the select transistor and are configured to sense and output respective signals indicative of levels of noise in the detector element.

Image sensor with stacked pixels including charge sharing gates

A chirped illumination LIDAR system having a transmitter that may include a pulsed radiation illuminator that is followed by a beam forming optics. The transmitter may be configured to output, during each illumination period of a sub-group of illumination periods, a first plurality of radiation pulses that form a decimated chirp sequence of radiation pulses; the decimated chirp sequence is a sparse representation of a chirp signal. A receiver of the system may be configured to receive, during each reception period of a sub-group of reception periods, one or more received light pulses from one or more objects that were illuminated by the one or more radiation pulses transmitted during each illumination period. The receiver may include multiple radiations sensing elements, multiple shutter circuits, and multiple processing circuits for converting the one or more received light pulses to output information; wherein the multiple shutter circuits may be configured to apply a shutter function on intermediate signals, the intermediate signals represent radiation sensed by the multiple radiations sensing elements, wherein the shutter function represents the chirp signal.

Chirped illumination LIDAR system

There is provided a device that includes a MOS transistor and a bias circuit coupled to the MOS transistor. The bias circuit is configured to bias the MOS transistor thereby maintaining the MOS transistor outside of saturation. The MOS transistor is configured to operate as a buffer or an amplifier, while being outside of saturation.

Noise reduction of a MOS transistor operating as an amplifier or buffer

A LIDAR system that may include a transmitter and a receiver. The LIDAR system may include a transmitter and a receiver that may include an array of neuromorphic pixels and multiple accumulators. Each neuromorphic pixel may include multiple subpixels, an analog adder and a comparator; wherein for each reception period the analog adder is configured to generate an analog adder signal by adding detection signals from subpixels that are expected to receive at least one received light pulse during the reception period; wherein for each reception period the analog adder signal is indifferent to subpixels that are not expected to receive any received light pulses during the reception period; and wherein the comparator is configured to provide pixel output signals by comparing the analog adder signal to a threshold. The multiple accumulators are configured to add multiple pixel output signals from neuromorphic pixels to provide, for each neuromorphic pixel, an accumulated signal that represents radiations sensed by the neuromorphic pixel during the multiple reception periods.

LIDAR system

A method for determining a temperature of a pixel; wherein the method includes supplying, by a current supply circuit and to the pixel, a bias current of a first value during a first period; changing, by the current supply circuit, a value of the pixel bias current to a second value; supplying, by the current supply circuit and to the pixel, a bias current of a second value during a second period; wherein the first value differs from the second value; reading, by a readout circuit that is coupled to the pixel, at a first point of time, a first output voltage of the pixel; wherein the first point in time occurs during the first period or the second period; and reading, by the readout circuit, at a second point of time that differs from the first point in time, a second output voltage of the pixel; wherein the second point in time occurs during the first period or the second period; wherein a difference between the first and second output voltage is indicative of a temperature of the pixel.

Estimating a temperature of a pixel

An ADC that includes a processing unit configured to receive from first sampling latches N first PWM pulse start counter values and N first PWM pulse end counter value, receive from second sampling latches, N second PWM pulse start counter values and N second PWM pulse end counter value; (c) select a counter that is coupled to a selected sampling latch; (d) calculate an estimated difference between first and second input analog signals based on at least readings of the selected latch. The readings of the selected counter include a first PWM pulse start counter value latched by the selected latch, a first PWM pulse end counter value latched by the selected latch, a second PWM pulse start counter value latched by the selected latch, and a second PWM pulse end counter value latched by the selected latch; and (e) output a digital output signal indicative of the estimated difference.

Analog to digital converter and a method for analog to digital conversion

An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.

A device comprising a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit; wherein the readout circuit comprises a current control circuit and a comparator; wherein the current control circuit is configured to (a) charge the current control circuit to a pixel affected charge using at least a pixel affected current that is indicative of an electrical parameter of the pixel and (b) drain, based on the pixel affected charge, a current control circuit current during a comparison period; wherein the comparator is configured to compare, during the comparison period, between a pixel affected voltage and a reference signal that changes during the comparison period and to provide at least one pulse that has is indicative of a value of the pixel affected voltage.

Compact readout circuit and a method for reading a pixel using a compact readout circuit

A device that may include a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit via coupling lines that comprises an output line and a reset line; wherein the readout circuit comprises (a) a comparator that is configured to track a coupling line electrical parameter to generate a pulse that is responsive to value of the electrical parameter, and (b) a pulse width to digital converter for outputting a digital output signal that is responsive to a width of the pulse.

Readout circuit coupled via a coupling line to a pixel and a method for reading a pixel using capacitance of the coupling line

A device that may include a pixel, an output conductor and a charge accelerator; wherein during a readout phase of the pixel, the pixel is configured to attempt to charge the output conductor to a pixel reset voltage and the charge accelerator is configured to perform a sampling operation and a charge operation; wherein during the sampling operation the charge accelerator is configured to sample a change in an output conductor voltage; wherein during the charge operation the charge accelerator is configured to output a charge accelerator output signal that is responsive to the change of the output conductor voltage, wherein once provided, the charge accelerator output signal accelerates a charging of the output conductor to a target voltage that is proximate to the pixel reset voltage; wherein the sampling operation and the charge operation do not overlap.

Fast reading of a pixel

An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; and a processor that is configured to generate an output digital signal that represents the input analog signal based on the PWM pulses.

A device comprising a pixel, a current source, and a readout circuit; wherein during a first readout phase of the pixel, the readout circuit is configured to sample a sampled output voltage of an output node of the pixel; and wherein an output current of the pixel is set by the current source; wherein between the first readout phase of the pixel and a second readout phase of the pixel, the pixel is configured to change the output current to provide a second output current, wherein the change of the output current is responsive to radiation sensed by a radiation sensor of the pixel during a sensing period; wherein during the second readout phase of the pixel the readout circuit is configured to sample the second output current while providing the sampled output voltage to the output node of the pixel; wherein during the first readout phase of the pixel and the second readout phase of the pixel a drain source voltage of an output transistor of the pixel is maintained constant; and wherein the output transistor is configured to generate the second output current.

Current mode pixel and readout circuit having a first and a second readout phase

A storage system, a non-transitory computer readable medium and a method for pre-fetching. The method may include presenting, by a storage system and to at least one host computer, a logical address space; determining, by a fetch module, to fetch a certain data portion from a data storage device to a cache memory of the storage system; determining, by a pre-fetch module, whether to pre-fetch at least one additional data portion from at least one data storage device to the cache memory based upon at least one characteristic of a mapping tree that maps one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space; and pre-fetching the at least one additional data portions if it is determined to pre-fetch the at least one additional data portions.

Growing community of inventors

Rishon Lezion, Israel

Vladimir Koifman