Texas Instruments Corporation

Massachusetts Institute of Technology

Compaq Computer Corporation, Inc.

Vladimir Bolkhovsky

Sameer P Pendharkar

John Lin

Henry Litzmann Edwards

Binghua Hu

Sheldon Douglas Haynie

Steven L Merchant

Howard S Lee

Taylor R Efland

Philip Leland Hower

Christopher W Leitz

Rabindra N Das

William D Oliver

Donna-Ruth Webb Yost

Mark A Gouker

Danna Rosenberg

James A Gregory

Kevin Ryu

David J Hover

Jonilyn L Yoder

Ann C Westerheim

Renee D Lambert

Tirunelveli Subramanian Sriram

Xhovalin Miloshi

John J Maziarz

Corey W Stull

A new process that enables void-free direct-bonded MBE-passivated large-format image sensors is disclosed. This process can be used to produce thin large-area image sensors for UV and soft x-ray imaging. Such devices may be valuable in future astronomy missions or in the radiology field. Importantly, by controlling the hydrogen concentration in the silicon oxide layers of the image sensor and the support wafer, voids in the bonding interface can be significantly reduced or eliminated. This process can be applied to any wafer that includes active circuitry and requires a second wafer, such as a support wafer.

Semiconductor surface passivation

A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called 'device') is provided as a substantially high quality factor, low loss superconducting device.

Superconducting integrated circuit

A double diffused region (), (), () is formed in a semiconductor substrate or in an epitaxial layer () formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

Method to manufacture LDMOS transistors with improved threshold voltage control

The concept of the present invention describes a semiconductor device with a junctionbetween a lightly doped regionand a heavily doped region, wherein the junction has an elongated portionand curved portions. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximityof the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

Premature breakdown in submicron device geometries

A double diffused region (), (), () is formed in an epitaxial layer (). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

Bladed silicon-on-insulator semiconductor devices and method of making

A method is described for forming an electromigration-resistant (ER) intermetallic region beneath and adjacent a conductive plug in a via. Preferably the ER region is formed of a sintered intermetallic compound of Al and Ti, and the conductive plug is formed of W.

Electromigration-resistant via structure

Growing community of inventors

Framingham, MA, United States of America

Vladimir Bolkhovsky