Agency for Science, Technology and Research

Unisantis Electronics Singapore Pte. Ltd.

Institute of Microelectronics

Vladimir Bliznetsov

Fujio Masuoka

Hiroki Nakamura

Shintaro Arai

Yisuo Li

Tomohiko Kudo

Xiang Li

Navab Singh

Zhixian Chen

Kavitha Devi Buddharaju

Nansheng Shen

King-Jien Chui

Yu Jiang

My The Doan

Ramana Murthy Badam

Chang Kuo Chang

Chi Fo Tsang

Xiaomei Bu

Qiang Guo

Moitreyee Mukherjee-Roy

Ahila Krishnamoorthy

The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

Surrounding gate transistor (SGT) structure

The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

Surround gate CMOS semiconductor device

Formation, through etching, of structures whose minimum width is less than can be achieved by optical means alone has been achieved by inserting a layer of sandwiching material between the photoresist (or hard mask if used) and the structure. By adjustment of the relative etch rates of this layer and the structure, a uniform lateral width reduction and surface smoothing of the structure is achieved.

Method to trim and smooth high index contrast waveguide structures

An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top corners of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.

Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects

A method of forming a via-first type dual damascene structure in the absence of an etch stop layer and without via-edge erosion or via-bottom punch-through is described. The invention uses two organic films deposited within via hole prior to trench etching. A via hole over a lower level metal line is first etched in the dielectric film. Two, preferably organic, bottom anti-reflective coating (BARC) films, first one being the conformal type to coat the surfaces and the walls of the via and the second one being the planarizing type to at least partially fill the via, are then deposited. Using a mask aligned to via hole, a wiring trench of desired depth is etched in the top portion of the dielectric film. During trench etching, the conformal BARC-1 film protects the via-edges from eroding and the planarizing BARC-2 film prevents punch-through of the via-bottom. Desired metal such as aluminum or copper are deposited within said dual damascene pattern.

Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC)

Growing community of inventors

Singapore, Singapore

Vladimir Bliznetsov