Intel Corporation

Vjekoslav Svilan

David N Mackintosh

Zeev Sperber

Naveen Kumar

Ron Gabor

Shantanu R Gupta

Michael Zelikson

Nadav Bonen

Kelvin Kwan

Norbert Unger

Jose A Baiocchi Paredes

Shai Rotem

Jawad Nasrullah

David Roger Ditzel

Naveen Neelakantam

Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain

In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

Performing local power gating in a processor

Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Method and systems for energy efficiency and energy conservation including on-off keying for power control

In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.

Managing dynamic capacitance using code scheduling

In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

Controlling power gate circuitry based on dynamic capacitance of a circuit

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Sunnyvale, CA, United States of America

Vjekoslav Svilan