Broadcom Corporation

Montana Systems Inc.

Vivian Chou

Sherman E Lee

John Lin

Charles T Aragones

Julien Lamoureux

A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.

Event-driven design simulation

An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.

An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.

A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other wireless device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one wireless device to receive inbound packetized audio data from the at least one wireless device and to transmit outbound packetized audio data to the at least one wireless device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC. The switch box enables the wireless transceiving integrated circuit to perform call conferencing operations, call forwarding operations, call hold operations, call muting operations, and call waiting operations.

Wireless local area network device supporting enhanced call functions

A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.

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Alhambra, CA, United States of America

Vivian Chou