Bull S.a.

Bull Sas

Vivian Blanchard

Marta Zorrilla

Dominique Rigal

Pierre Axel Lagadec

Laurent Marliac

Disclosed is a method for test traffic generation, at test-sending switches for a network of calculation nodes, and of inspection of this test traffic, at test-receiving switches of this network, including: the generation and sending of test traffic, at least at a selected test-sending input or output port of one selected test-sending switch, sent to at least one selected test-receiving input or output port of a selected test-receiving switch, where the test traffic is generated and sent by a traffic generation component configured as an additional input of the selected test-sending input or output port, where the test traffic is inspected by a traffic inspection component configured for filtering the output of the selected test-receiving input or output port.

Method for test traffic generation and inspection, and associated switch input or output port and switch

The invention relates to an automated method for inserting dummy surfaces () into the various layers of the physical design () of multilayer integrated circuits organized in interconnected units () containing interconnected blocks () composed of interconnected cells (), implemented by an integrated circuit design system (). The multilayer integrated circuit design (), stored in the design system () is implemented layer by layer, through selective insertion of patterns of dummy surfaces (), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design () of the integrated circuits, by means of individual implementation of the interconnected blocks () and first interconnection routing () for said interconnected blocks () and individual implementation of the interconnected units () and second interconnection routing () for said interconnected units (). The patterns of dummy surfaces are established selectively in accordance with the design of the blocks () of the integrated circuit.

Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit

An automated method for inserting dummy surfaces into the various layers of the physical design of a multilayer integrated circuit is implemented by an integrated circuit design system. The integrated circuit is organized in interconnected units containing interconnected blocks composed of interconnected cells. The multilayer integrated circuit design, stored in the design system is implemented layer by layer, through selective insertion of patterns of dummy surfaces. The selective insertion is based on an insertion hierarchy with respect to the hierarchy of the physical design of the integrated circuit, by means of individual implementation of the interconnected blocks and first interconnection routing for said interconnected blocks and individual implementation of the interconnected units and second interconnection routing for said interconnected units. The patterns of dummy surfaces are established selectively in accordance with the methods used for designing the blocks of the integrated circuit. The methods used for designing the interconnected blocks include a standard cell method and a custom cell method.

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Saint Germain-en-Laye, France

Vivian Blanchard