Intel Corporation

Microsoft Technology Licensing, LLC

Vivek Tiwari

David J Ayers

Edward Thomas Grochowski

Abhishek R Appu

Elmoustapha Ould-Ahmed-Vall

Sayan Lahiri

Ian A Young

Kamal Sinha

David J Sager

James M Holland

Pattabhiraman K

Radhakrishnan Venkataraman

Subramaniam M Maiyuran

Peter L Doyle

Chandrasekaran Sakthivel

Daniel Pohl

Devan Burke

Philip R Laws

James Steven Burns

David M Brooks

Joydeep Ray

Travis T Schluessler

Stefan Rusu

Ankur N Shah

Nikos Kaburlasos

Kai Xiao

John H Feit

Deepak Shashidhar Vembar

Jacek Kwiatkowski

Carson Brownlee

Jefferson Amstutz

Marsha Eng

Balaji Vembu

Josh B Mastronarde

Vinod Sharma

Sudarshan Kumar

Kenneth D Shoemaker

Suri B Medapati

Sivakumar Makineni

Kirill Sergeyevich Lebedev

Tom E Wang

Devang Jaysinh Negandhi

Zhenrong Qian

Sanjay Bysani

Mahesh Gupta

Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

Dynamic brightness and resolution control in virtual environments

A method and system for reviewing edits and editing content items are provided. An edit to a first version of a first content item is received. The first version of the first content is part of the active content delivery campaign and has been delivered over a computer network to a first plurality of computing devices. The edit is stored in a first storage that is separate from a second storage. An event indicating the edit is inserted into an event processing system. A result approving the edit is received from the event processing system. In response to receiving the result approving the edit, a second version is caused to be stored in the second storage. The second version reflecting the edit is caused to be delivered over the computer network.

Editing mechanism for electronic content items

An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed.

Adjusting graphics rendering based on facial expression

An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed.

Adaptive multi-resolution for graphics

A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

Mechanism for estimating and controlling di/dt-induced power supply voltage variations

A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Method and apparatus to limit current-change induced voltage changes in a microcircuit

A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the scaled activity. If the power state reaches a first threshold, the operating point of the processor is adjusted and a new scaling factor is selected to determine the power state.

Digital throttle for multiple operating points

A mechanism is disclosed for determining a voltage at a device in a power delivery network. The mechanism includes determining an impulse response for the power delivery network, and tracking the current consumed by the device as it operates over a sequence of clock cycles. The activity profile is filtered using a representation of the impulse response to provide a profile of the voltages at the device.

Simulation of di/dt-induced power supply voltage variation

A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline, and to determine a power state for the processor from the monitored activity. One of two or more power control mechanisms is engaged, responsive to the power state of the processor reaching a threshold.

Multiple mode power throttle mechanism

The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processor's functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.

Mechanism to control di/dt for a microprocessor

A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.

Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages

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San Jose, CA, United States of America

Vivek Tiwari