Broadcom Corporation

Cirrus Logic Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Vivek Telang

Afshin Momtaz

Velu Pillai

Sudeep Bhoja

Ali Ghiasi

Vasudevan Parthasarathy

Chung-Jue Chen

Jun Cao

Magesh Valliappan

Lorenzo Longo

Hong Chen

Namik Kocaman

Sundararajan Chidambara

Vasudevan Parthasarthy

Michael Furlong

Howard A Baumer

Eric B Smith

Stephen Timothy Hodapp

Kang Xiao

Anthony Brewster

A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an 'overclocked' NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Overclocked line rate for communication with PHY Interfaces

A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an 'overclocked' NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Overclocked line rate for communication with PHY interfaces

A system, method and apparatus for multi-lane auto-negotiation over reduced-lane media. Auto-negotiation over an M-lane communication interface can be coordinated with the auto-negotiation over an N-lane communication interface, wherein M&#x3e;N. A recursive-type auto-negotiation process would begin with the M-lane communication interface and be prevented from completing until the auto-negotiation process over the N-lane communication interface completes.

System, method and apparatus for multi-lane auto-negotiation over reduced lane media

A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.

Use of multi-level modulation signaling for short reach data communications

According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Multi-protocol communications receiver with shared analog front-end

An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.

Adaptive offset adjustment algorithm

A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider.

Multi-channel multi-protocol transceiver with independent channel configuration using single frequency reference clock source

Various embodiments are disclosed relating to crosstalk emission management. In an example embodiment, an amplitude of a main tap of a transmit equalizer may be determined to limit crosstalk emitted from a local channel to one or more other channels to be less than a threshold. A ratio of an amplitude of at least one secondary tap of the transmit equalizer to the amplitude of the main tap may be determined to provide equalization to the local channel.

Crosstalk emission management

An apparatus is disclosed that includes first transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a first Ethernet communication protocol at a first data rate, second transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a second Ethernet communication protocol at a second data rate; and third transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a third Ethernet communication protocol at a third data rate.

Multi-rate backplane transceiver

Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter ('ADC') block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery

Embodiments include a system for performing electronic dispersion compensation on an information-bearing signal transmitted over a communication channel. The system may include a channel identification module configured to receive a first digitized version of the information bearing signal and an equalized version of the information-bearing signal, and may be configured to determine an impulse response of the communication channel based thereon. The system may include a time varying phase detector configured to receive the equalized version of the information bearing signal, a second digitized version of the information-bearing signal, and the impulse response, and may be further configured to generate a reference wave based on the impulse response and the equalized version of the information-bearing signal. The time varying phase detector may be configured to generate a phase signal based on the reference wave and on an error signal determined from the reference wave and the second digitized version of the information-bearing signal.

Growing community of inventors

Austin, TX, United States of America

Vivek Telang