Texas Instruments Corporation

Vivek Swaminathan Sridharan

Christopher Daniel Manack

Salvatore Frank Pavone

Patrick Francis Thompson

Joseph O Liu

Nazila Dadvand

Rajen Manicon Murugan

Yiqi Tang

Liang Wan

Hiep Xuan Nguyen

Qiao Chen

Jonathan Andrew Montoya

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

Efficient redistribution layer topology

A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

Method of forming brass-coated metals in flip-chip redistribution layers

A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

Integrated system-in-package with radiation shielding

A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

Semicondutor package substrate with die cavity and redistribution layer

In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

Wafer chip scale packages with visible solder fillets

A package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. The package is a wafer chip scale package (WCSP). The package further includes a solder ball attached to the redistribution layer.

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Dallas, TX, United States of America

Vivek Swaminathan Sridharan