Agere Systems Inc.

Agere Systems Guardian Corp.

Vivek Saxena

Sudhanshu Misra

Pradip Kumar Roy

Donald Thomas Cwynar

John Michael Sharpe

Sundar Srinivasaan Chetlur

Dennis Okumu Ouma

Sailesh Mansinh Merchant

William Graham Easter

Nace Layadi

Sundar Srinivasan Chetlur

Seungmoo Choi

Sidhartha Sen

Amal Ma Hamad

Minesh Amrat Patel

Felix Llevada

Mahjoub Ali Abdelgadir

Pei H Yih

Paul Yih

A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiO , where x is preferably less than 2.

Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics

A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout regions overlying the semiconductor substrate. Each layout region will comprise an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacturing. Each dummy fill region in each layout region will have a different density with respect to other dummy fill regions in other layout regions, so that the combined density of the active interconnect feature region and the dummy fill feature region in a layout region will be substantially uniform with respect to a similar combined density in each of the other layout regions.

Semiconductor device having an interconnect layer with a plurality of layout regions having substantially uniform densities of active interconnects and dummy fills

The present invention provides a method of manufacturing an integrated circuit including planarizing a semiconductor wafer surface. In one embodiment, the method comprises forming a dielectric layer over a first level having an irregular topography, depositing a sacrificial material over the dielectric layer, and then planarizing the semiconductor wafer surface to a planar surface. More specifically, the dielectric layer forms such that it substantially conforms to the irregular topography of the first level. The sacrificial material is formed to a substantially planar surface over the dielectric layer. Thus, the sacrificial material provides a substantially uniform chemical/mechanical planarization (CMP) process removal rate across the semiconductor wafer surface. In the ensuing step, planarizing the semiconductor wafer surface to a planar surface removes the sacrificial material and a portion of the dielectric layer with a CMP process.

Method for chemical/mechanical planarization of a semiconductor wafer having dissimilar metal pattern densities

The present invention provides a method of manufacturing a resistor for use in a memory element and a semiconductor device employing the resistor. The method of manufacturing may comprise forming a dielectric layer over an active region of a semiconductor wafer and forming a resistive layer on the dielectric layer. The resistive layer comprises a compound wherein a first element of the compound is a Group III or Group IV element and a second element of the compound is a Group IV or Group V element. The method further comprises connecting an electrical interconnect structure to the resistive layer that electrically connects the resistive layer to the active region.

High resistivity film for 4T SRAM

A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.

Methods for deuterium sintering

A polishing fluid comprising a distributed organic phase and a continuous aqueous phase, each phase comprising at least one complexing agent. The aqueous phase also having abrasive particles dispersed therein. Reaction products generated during polishing interact with the aqueous phase complexing agent to form water soluble metallic complexes, the water soluble metallic complexes diffuse to an organic/water interface where they release complexing agent molecules in the aqueous phase and generate metal ions which interact with the organic phase complexing agent to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.

Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method

A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.

Method for making an interconnect layer and a semiconductor device including the same

Growing community of inventors

Orlando, FL, United States of America

Vivek Saxena