Skyworks Solutions, Inc.

Silicon Laboratories Inc.

Texas Instruments Corporation

Vivek Sarda

Harihara Subramanian Ranganathan

Pio Balmelli

Zhuo Fu

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

FSYNC mismatch tracking

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

Data protocol over clock line

A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Secondary phase compensation assist for PLL IO delay

A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Secondary phase compensation assist for PLL IO delay aligning sync signal to system clock signal

Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.

Maintaining a virtual time of day

In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.

Maintaining the correct time when counter values are transferred between clock domains

A delay circuit provides a programmable delay and includes an input selector circuit to select between a loop delay output signal and an input signal. A loop delay circuit provides a loop delay to the input signal and supplies the loop delay output signal. The input signal can be recirculated through the loop delay circuit to extend the range of the delay. The input selector circuit selects the feedback signal during recirculation. A variable delay circuit provides a variable delay to the loop delay output signal after the recirculation is complete and supplies a variable delay output signal. An output selector circuit selects the output of the output selector circuit during the recirculation and selects the variable delay output signal after the recirculation is complete to thereby provide a delayed signal with the delay based on the loop delay, the number of loops of recirculation, and the variable delay.

Signal delay control using a recirculating delay loop and a phase interpolator

A line card in a network box receives a SyncE clock signal and an input synchronization (SYNC) signal. A phase-lock loop (PLL) in the line card receives the SyncE clock signal as a reference clock signal and generates an output SyncE clock signal. The line card regenerates a SYSCLK signal using a digitally controlled oscillator that receives a timing signal from the SyncE PLL and receives a control signal from control logic on the line card. The frequency and phase information contained in the SYNC signal is utilized to control the DCO. The SYSCLK signal is divided to generate an output SYNC signal. The control logic uses the time difference between the input SYNC signal and a SYNC feedback signal to control the DCO to provide a zero delay SYNC output signal. The output SYNC signal and the SYSCLK signal control a time of day counter in the line card.

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Austin, TX, United States of America

Vivek Sarda