Cirrus Logic Inc.

Apple Inc.

Vivek Oppula

Bhoodev Kumar

Muraleedharan Ramakrishnan

John L Melanson

Willem Zwart

Thomas H Hoff

Gus P Ikonomopoulos

Anuradha Parsi

Qi Cai

Anindya Battacharya

Niju Alex Geevarughese

Benoit M Jubelin

Techniques are disclosed relating to power control and voltage margining. In some embodiments, first and second component circuits operate based on a supply voltage generated by a power supply. Voltage sensor circuitry may generate voltage measurements. Voltage margin control circuitry may determine a voltage ceiling based on a current operating state of the first component circuit and a current operating state of the second component circuit. The control circuitry may transmit control signals to the power supply to incrementally reduce the supply voltage until detecting a low-supply-voltage condition based on a voltage measurement generated by the voltage sensor circuitry. Disclosed techniques may advantageously provide voltage margin while reducing overall power consumption.

Adaptive voltage margin techniques

An apparatus for biasing a plurality of microphones includes a sensing circuit that actively senses a local ground reference for each microphone. An intermediate stage receives a constant non-local reference voltage as an input and responsively provides a respective constant local reference signal (e.g., current) with respect to each of the actively sensed local ground references. For each microphone, a respective microphone bias block uses the respective constant local reference signal to generate a respective constant local microphone bias voltage to bias the microphone. For each microphone, a variable RC network uses the respective constant local reference current to generate a constant local reference voltage for the microphone. Each RC network is controllable in response to the respective actively sensed local ground reference to independently set the respective local microphone bias voltage. A sensing circuit may actively sense the local microphone bias voltages to control local microphone bias voltage generation.

Microphone bias apparatus and method

Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.

Synchronous differential signaling protocol

A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

Synchronous, internal clock edge alignment for integrated circuit testing

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Austin, TX, United States of America

Vivek Oppula