Intel Corporation

Micron Technology Incorporated

Other

Vivek K De

Yibin Ye

Muhammad M Khellah

Dinesh Somasekhar

James W Tschanz

Siva G Narendra

Ali Keshavarzi

Stephen H Tang

Fabrice Paillet

Tanay Karnik

Shih-Lien L Lu

Gerhard Schrom

Peter Hazucha

Shekhar Yeshwant Borkar

Jaydeep P Kulkarni

Nam Sung Kim

Sriram R Vangal

Krishnan Ravichandran

Christopher B Wilkerson

Harish Krishnamurthy

Bibiche M Geuskens

Xiaosen Liu

Donald S Gardner

Nitin Y Borkar

Vaibhav Vaidya

Arijit Raychowdhury

Brian S Doyle

Suman Datta

Ram K Krishnamurthy

Fatih Hamzaoglu

Turbo Majumder

Keith A Bowman

Christopher Schaef

Nachiket Venkappayya Desai

Suhwan Kim

Mohsen Alavi

Khondker Z Ahmed

Robert S Chau

Ming Lei Zhang

Nasser A Kurd

Steven Hsu

Krishnamurthy Soumyanath

Rajendran Nair

Antonio Gonzalez

Xavier Vera

Javed Sabir Barkatullah

Javier Carretero Casado

Jaume Abella

Pedro Chaparro Monferrer

Mircea R Stan

Victor Zia

Howard A Wilson

David W Bruneau

Hong Wang

Per H Hammarlund

Kevin X Zhang

Juanita N Kurtin

Asit K Mallick

Belliappa Manavattira Kuttanna

Ethan Schuchman

Gunjan H Pandya

Moty Mehalel

George Shchupak

Badarinath N Kommandur

Stephen H Gunther

Charles Augustine

Amit Agarwal

Jianping Xu

Robert Milstrey

Vaughn J Grossnickle

Pascal Meinerzhagen

Scott Chiu

Bo Zheng

Sung Tae Moon

Pascal A Meinerzhagen

Sanu K Mathew

Narayan Srinivasa

Sudhir K Satpathy

Raghavan Kumar

Mark A Anders

Vikram B Suresh

Gregory Kengho Chen

Himanshu Kaul

Alaa R Alameldeen

Joseph Shor

Kaushik Roy

Manoj Sachdev

Atila Alvandpour

Pavan Kumar

Liqiong Wei

Yatin Hoskote

Sandip Kundu

Cyrille Dray

David M Wu

Chris Wilkerson

Subhasish Mitra

Stephen Kim

Farzin Guilak

Timothy L Deeter

Daniel S Klowden

An integrated circuit (IC) is provided for in-situ anomaly detection. Sensors in the IC generates sensor datasets including information indicating conditions in the IC. A processing unit in the IC uses a sensor dataset and a model to detect and classify the anomaly. The processing unit may filter the sensor dataset, extract features from the filtered sensor dataset, and input the features into the model. The model outputs one or more classifications of the anomaly. A feature may be a distance vector that represents a difference between a data value in the filtered sensor dataset from a reference data value. The model may be a network of bit-cells in the IC. The model may be continuously trained in-situ, i.e., on the IC. The processing unit may provide the classifications to another processing unit in the IC. The other processing unit may mitigate the anomaly based on the classifications.

In-situ detection of anomalies in integrated circuits using machine learning models

A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.

Apparatus and method for approximate trilinear interpolation for scene reconstruction

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.

System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor

A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

Non-linear clamp strength tuning method and apparatus

Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

Multiple output voltage conversion

Circuitry is provided to control a performance level of a processing device depending on two or more operating points of the processing device. An operating point has a corresponding frequency and a corresponding voltage. The performance-level control circuitry arranged to cross-multiply parameters corresponding to a first operating point and a second, different operating point of the processing device. A relative energy expenditure of the first operating point and the second operating point is determined based on the cross multiplication. An operating point of the processing device is selected depending on the determined relative energy expenditure. An apparatus having the performance level control circuitry, machine readable instructions for implementing the performance level control and a corresponding method are also provided.

Controlling a processing performance level depending on energy expenditure

Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.

Energy harvester with multiple-input multiple-output switched-capacitor (MIMOSC) circuitry

Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

Physically unclonable function implemented with spin orbit coupling based magnetic memory

Techniques and mechanisms for changing a consistency with which a cell circuit ('cell') settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

Device, system, and method to change a consistency of behavior by a cell circuit

A minimum delay error apparatus such as a minimum delay error detection, prediction, correction, repair, prevention, and/or avoidance apparatus includes a minimum delay path replica circuit. The minimum delay path replica circuit can detect or predict, and subsequently can correct or avoid, minimum delay errors in data paths of digital circuits using pulsed latches.

Minimum delay error detection and correction for pulsed latches

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Beaverton, OR, United States of America

Vivek K De