Intel Corporation

Vivek Joy Kozhikkottu

Shankar Ganesh Ramasubramanian

Dinesh Somasekhar

Melin Dadual

Wei Wu

Suresh S Chittor

Esha Choukse

Kon-Woo Kwon

Kuljit Singh Bains

Wei P Chen

Rajat Agarwal

Alaa R Alameldeen

Jongwon Lee

Ashish Ranjan

Sai Prashanth Muralidhara

Hussein Alameer

Jon Stephan

Aravinda K Radhakrishnan

A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a 'swap' manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.

Two-level main memory hierarchy management

A device includes a driver circuit to send data bits onto a data bus that is partitioned into a DC component and an AC component. The driver circuit is to, for some data bits, retrieve a value of a DC power ratio of the data bus. The driver circuit is further to determine, using the value of the DC power ratio, a first value for a first portion of total power to be dissipated over the DC component to transmit the data bits, and determine, using one minus the value of the DC power ratio, a second value for a second portion of total power to be dissipated over the AC component to transmit the data bits. The driver circuit is to determine whether to send the data bits onto the data bus using data bus inversion dependent on a combination of the first value and the second value.

Programmable data bus inversion and configurable implementation

Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.

Techniques for setting a 2-level auto-close timer to access a memory device

An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

Memory device with local cache array

In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

System, apparatus and method for application specific address mapping

An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.

Fast search of error correction code (ECC) protected data in a memory

Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.

Error correction code (ECC) and data bus inversion (DBI) encoding

Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.

Minimal aliasing bit-error correction code

In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

Low latency statistical data bus inversion for energy reduction

Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.

Low-overhead mechanism to detect address faults in ECC-protected memories

An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.

Growing community of inventors

Hillsboro, OR, United States of America

Vivek Joy Kozhikkottu