Globalfoundries Inc.

Vivek Joshi

Sriram Balasubramanian

Randy W Mann

William McMahon

Yoann Mamy Randriamihaja

Chad Weintraub

Ratheesh Ramachandran Thankalekshmi

A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response

At least one method, apparatus and system disclosed involves testing a dual port memory cell in a memory device. A semiconductor wafer is processed for providing a dual port memory device. An inline DC contention margin test is performed for testing a contention margin related to a write operation into a cell of the memory device. A determination is made as to whether the contention margin is within a predetermined range. A responsive action is performed in response to determining that the contention margin is outside the predetermined range.

Methods, apparatus and system determining dual port DC contention margin

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San Jose, CA, United States of America

Vivek Joshi