Intel Corporation

Vivek Garg

Krishnakanth Venkata Sistla

Ankush Varma

Eric J DeHaemer

Ian M Steiner

Malini Krishnan Bhandaru

Scott P Bobholz

Raghunandan Makaram

Martin Rowland

Nikhil Gupta

William Johnson Bowhill

Subramaniam M Maiyuran

Avinash N Ananthakrishnan

Dean A Mulla

Venkatesh Ramamurthy

Deep K Buch

Corey D Gough

Ripan Das

Efraim Rotem

John Joseph Browne

Chris MacNamara

Vasudevan Srinivasan

Nagasubramanian Gurumoorthy

Matthew M Bace

Mark Rowland

Jagannath Keshava

Sujal A Vora

David P Lerner

Joseph M Sullivan

Ankur N Shah

Alexander Gendler

Rajeev K Nalawadi

James Steven Burns

Chris Poirier

Matthew B Callaway

James Varga

Eric Dehaemer

Eliezer Weissmann

Stephen H Gunther

Alon Naveh

Jeremy J Shrall

Inder M Sodhi

Tessil Thomas

Ganapati Srinivasa

Ashish V Choubal

Ramamurthy Krithivas

Phanindra Mannava

Rakesh Kumar

Binata Bhattacharyya

Jeffrey D Gilbert

Daniel G Borkowski

Ling Cen

Adwait Purandare

Don Soltis

Satish Shrimali

Lokesh Sharma

Cesar A Quiroz

Mohammad A Abdallah

Andrew J Herdrich

Nadav Shulman

Eugene Gorbatov

Guy M Therien

Nir Rosenzweig

Russell Jerome Fenger

Vladimir M Pentkovski

Viktor D Vogman

Salvador Palanca

Sandeep Ahuja

Larisa Novakovsky

Bharat S Pillilli

Reid James Riedlinger

Guy G Sotomayor

Edward R Stanford

Liang Yin

Arvind Raman

Brian J Griffith

Robin A Steinbrecher

Eswaramoorthi Nallusamy

Nazar Syed Haider

Phani Kumar Kandula

Ariel Szapiro

Susan F Smith

Erik Hallnor

Monica Gupta

Rahul Agrawal

Yogesh Bansal

Vijay Dhanraj

Nimrod Angel

Suresh Chemudupati

Kimberly C Weier

Ido Melamed

Elkana Korem

Chandra P Joshi

Aman Sewani

Arye Albahari

Nir Misgav

Chung-Chi Wang

Rupal Parikh

Nilanjan Palit

Joseph R Doucette

In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

Register interface for computer processor

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

Apparatus and method for processing virtual graphics processor telemetry data based on quanta. For example, one embodiment of a graphics processing apparatus comprises virtualization control circuitry to virtualize graphics processing resources of one or more graphics processing units (GPU), wherein one or more virtual machines (VMs) are to be provided with controlled access to the graphics processing resources in accordance with a current graphics virtualization configuration specified, at least in part, in one or more virtualization control registers of the virtualization control circuitry; a scheduler to schedule each VM for processing by the graphics processing resources in accordance with the graphics virtualization configuration, the scheduler to generate a VM switch event responsive to each VM being scheduled for processing on the graphics processing resources; power management circuitry to collect telemetry data associated with VMs which have temporarily completed processing on the graphics processing resources and to forward the telemetry data to a telemetry data aggregator, the telemetry data aggregator to combine telemetry data collected for each VM over a period of time and to store per-VM telemetry data in a data repository accessible by a virtualization management application.

Apparatus and method for processing telemetry data in a virtualized graphics processor

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states

Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.

Techniques to dynamically enable and disable accelerator devices in compute environments

Configuring power management functionality in a processor

In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

Thread scheduling using processing engine information

A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.

Systems, methods and devices for using thermal margin of a core in a processor

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Folsom, CA, United States of America

Vivek Garg