Cadence Design Systems, Inc.

Vivek Chickermane

Krishna Chakravadhanula

Brian Edward Foutz

Shaleen Bhabu

Senthil Arasu Thirunavukarasu

Patrick Gallagher

Paul Alexander Cunningham

Steev Wilcox

Christos Papameletis

Sandeep Bhatia

Dale Meehl

Rajesh Khurana

Brion L Keller

Jagjot Kaur

Ankur Gupta

Manish Pandey

Pinhong Chen

Qi Wang

Huan-Chih Tsai

Christina Chu

Steven Sharp

Steven Lee Gregor

Yonghao Chen

Sagar Kumar

Subhasish Mukherjee

Sarthak Singhal

Louis Christopher Milano

Priyanka Dasgupta

David George Scott

Nitin Parimi

Divyank Mittal

Prateek Kumar Rai

Puneet Kumar Arora

Sameer Chakravarthy Chillarige

Akhil Garg

Mitchell W Hines

Richard Schoonover

Sahil Jain

Karishna Chakravadhanula

Bharath Nandakumar

Pradeep Nagaraj

Gopi Kudva

Dhruv Dua

Carl Barnhart

Pratyush Aditya Kothamasu

Bambuda Chen Chien Leung

James Sage

Susan Marie Genova

Xiaochuan Yuan

Yonghoa Chen

Balveer Singh Koranga

The present disclosure relates to reducing power consumption of test point circuit elements of an integrated circuit (IC) design. An ungated input clock for at least one testing point circuit element for the IC design can be identified. The IC design can be updated by coupling a test point clock gating circuit element to a clock gate input node of the IC design that is to receive the ungated input clock, to the at least one test point circuit element, and to a test mode signal generation element that is to provide a test mode signal to create an updated IC design. The test point clock gating circuit element can be enabled and disabled based on a logical value of the test mode signal to control a supply of the ungated input clock to the at least one testing point circuit element.

Systems and methods for reducing test point power consumption in a circuit design

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.

Clock-based test-point flop sharing in a circuit design

An integrated circuit (IC) chip includes an intellectual property (IP) core that executes logical operations to perform a function. The IC chip also includes a core wrapper logically encapsulating the IP core such that inputs and outputs to the IP core are funneled through ports of the core wrapper. The IC chip further includes a locking mechanism for controlling communications with the core wrapper. The locking mechanism includes a set of locking elements that gate access to the ports of the wrapper and a lock interface that controls a state of the set of locking elements based on a presence or absence of an authentication key.

Locking mechanism and core wrapping for IP core

An integrated circuit (IC) chip includes an intellectual property (IP) core that executes logical operations to perform a function. The IC chip also includes a scan chain array for testing the IP core, and a pseudo random pattern generator (PRPG) that provides a pseudo random pattern based on a seed. The IC chip includes a spreader network that applies a first pseudo random code to a first edge of a die of the IC chip and a second pseudo random code to a second edge of the die of the IC chip in response to the pseudo random pattern and combines the first and second code to form a 2D code that is applied to the scan chain array. A security signature register of the IC chip outputs a signature corresponding to a response from the scan chain array that is employable to detect changes to an IC design.

IC chip with IC design modification detection

Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.

3D stacked die testing structure

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

Test-point flop sharing with improved testability in a circuit design

An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

IC chip test engine

A scan chain engine can determine a set number of EXTEST scan chains for the IP block and based on a predetermined maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine iteratively executes partitioning on the IP block to generate a set of partitions. Each partition in the set of partitions has a number of EXTEST wrapper cells that does not exceed the maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine selectively merges partitions of the set of partitions to form a set of populated partitions that each include an EXTEST wrapper cell. The number of partitions is equal to the set number of EXTEST scan chains for the IP block. The scan chain engine generates wire paths connecting EXTEST wrapper cells of each populated partition to construct the set number of EXTEST scan chains for the IP block.

IP block scan chain construction

Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time ('TAT'), test data volume, tester memory and cost associated with design for test ('DFT'), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

Method to improve testability using 2-dimensional exclusive or (XOR) grids

Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.

Compacting test patterns for IJTAG test

Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).

Low-power shift with clock staggering

Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

Method for optimally connecting scan segments in two-dimensional compression chains

A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.

Test circuitry with annularly arranged compressor and decompressor elements

Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

Devices and methods for test point insertion coverage

Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.

2D compression-based low power ATPG

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Ithaca, NY, United States of America

Vivek Chickermane