Cadence Design Systems, Inc.

Vivek Bhardwaj

Oleg Levitsky

Dinesh Gupta

Didier Seropian

In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs

Methods for single pass parallel hierarchical timing closure of integrated circuit designs

In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Methods for generating a user interface for timing budget analysis of integrated circuit designs

Systems for single pass parallel hierarchical timing closure of integrated circuit designs

User interface for timing budget analysis of integrated circuit designs

Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs

Growing community of inventors

New Delhi, India

Vivek Bhardwaj