Honeywell Information Systems Italia

Honeywell Information Systems Inc.

Vittorio Zanchi

Tiziano Maccianti

Ferruccio Zulian

An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer. The microinstruction transfer speed from working memory to the processor is further enhanced by means of different timing for the data transfer through the bus and the microinstruction transfer through the bus. In the case of data transfer a bus access cycle is started at the end of the processor cycle during which the relevant bus interface register is loaded. In the case of microinstruction read out from working memory, the additional interface register is loaded at the beginning of a processor cycle concurrently with the request of bus access cycle, so that the two overlap.

Asynchronous bus multiprocessor system

Sequencer means for a microprogrammed control unit which develops consecutive addresses of microprograms, branches to subroutines with address saving and possible return to microprogram, as well as interrupting microprogram forcings with address saving of the interrupted microprograms. In order to allow the double saving of microprogram and subroutine addresses in case of concurrent interruptions and branches, the sequencer means is provided with two address generation loops each including a register. The two loops have a common portion to which they accede through a multiplexer. The first loop is further coupled to a saving register stack. While the first loop executes the saving of a microprogram address and the latching or a branch address received from the second loop, the second loop executes a first updating and related latching or interrupting microprogram address. During the following cycle, by command of the first microinstruction of the interrupting microprogram, the second loop performs a first updating and related latch of the interrupting microprogram address and the first loop saves into the register stack the branch address and performs a second updating and related latching of the interrupting microprogram address.

Sequencer means for microprogrammed control unit

A system comprising interface circuits for coupling together for bidirectional information communication the various units of a data processing system, wherein such communication is effected by a totally interlocked bidirectional dialogue carried out over a single lead, but utilizing signals transmitted on another lead of the interface for clearing the interface circuits associated with the single lead.

System for bidirectional transmission of interlocked signals

An interrupt handling apparatus for a data processing system comprising a plurality of processing units and a working memory to which the units may access through a common bus by means of multilevel priority or access requests. Access requests are forwarded by each unit to a bus access controller preferably made part of the working memory through a single lead for each unit, irrespective of the access request priority level; and if the priority level of an access request is high, a high priority level access request signal is distributed by the high priority level interrupting unit to the other system units, which mask their possible access request of a lower priority level in response to such signal. The bus access controller grants access to a unit at a time on a priority basis determined by a priority network in the controller totally insensitive to any priority level difference of the access requests.

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Milan, Italy

Vittorio Zanchi