Stmicroelectronics S.r.l.

Vittorio Peduto

Claudio Diazzi

Giancarlo Zinco

Pietro Gallina

Giancarlo Saba

Luca Battaglin

Mauro De Ponti

Simone Gardella

Marco Ferretti

Domenico Pedrali

Fabio Brognara

Giacomo Ardissono

The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.

Electronic circuit for highly efficient driving of piezoelectric loads

The present invention relates a system adapted to localize and remove software type errors comprising a microcontroller () and storing means (), said microcontroller () being connected to said storing means () by a serial type bus (), characterized in that said system comprises a first () and a second () converter, said first converter () being inside said microcontroller () and said second converter () being inside said storing means (), said first () and second () converter being connected by means of said serial type bus (), said storing means () being outside said microcontroller (), said microcontroller () adapted to transmit and to receive data with said storing means () by means of said first () and second () converter.

System for finding and removing errors using a serial bus for a microcontroller

A method for generating sequences of memory addresses for a memory buffer having N*M locations includes making a first address and a last address of every sequence respectively equal to 0 and to N*M&#x2212;1, assigning a first sequence of addresses, and each address but a last address of another sequence of addresses is generated by multiplying a corresponding address of a previous sequence by N, and performing a modular reduction of this product with respect to N*M&#x2212;1. The method further includes calculating a greatest bit length of every address, and calculating an auxiliary constant as the modular reduction with respect to N*M&#x2212;1 of the power of two raised to twice the greatest bit length. Each sequence of addresses includes storing an auxiliary parameter equal to an N+1address of the current sequence, computing a first factor as the modular product with respect to N*M&#x2212;1 of the auxiliary constant based upon a ratio between the auxiliary parameter and the power of two raised to the greatest bit length, and generating all addresses but the last of a sequence by performing the Montgomery algorithm using the first factor and an address index varying from 0 to N*M&#x2212;2 as factors of the Montgomery algorithm, and with the quantity N*M&#x2212;1 as modulus of the Montgomery algorithm, and the greatest bit length as the number of iterations of the Montgomery algorithm.

Method and circuit for generating memory addresses for a memory buffer

A circuit for driving capacitive loads in a highly efficient manner. In one embodiment, a drive portion is connected to at least one end of a capacitive electric load being applied a voltage waveform. The embodiment further comprises a switching circuit portion having its output connected to the above one end of the capacitive load in order to supply a fraction of the overall current demanded by the load. Additionally, a switching circuit and accompanying switching method provide for efficiently supplying peak current to the capacitive load during voltage fluctuation in the voltage waveform. Briefly, the invention is a circuit arrangement aimed at providing a highly efficient drive for the capacitive load, using a combined linear/switching setup and without distorting the quality of the waveform generated across the capacitive load.

High-efficiency driver circuit for capacitive loads

A method of driving an inductive load connected to an output of a power stage includes comparing a signal representative of an instantaneous value of current flowing through the inductive load with upper and lower thresholds during a switching cycle. The method also includes alternately performing a magnetization phase during which current is forced through the inductive load, and a demagnetization phase during which a load inductance of the inductive load discharges through at least one of a slow recirculation discharge current path and a fast recirculation discharge current path. Switching is performed between the slow and fast recirculation discharge current paths during each switching cycle as a function of the comparison for reducing a ripple on an output signal from the power stage.

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Ivrea, Italy

Vittorio Peduto