Silicon Laboratories Inc.

Integration Associates Incorporated

Vitor Pereira

Mustafa H Koroglu

Jeffrey A Tindle

Arup Mukherji

Terry Lee Dickey

Michael Johnson

Rangakrishnan Srinivasan

Zhongda Wang

Abdulkerim Coban

Ruifeng Sun

Tiago Marques

Sriharsha Vasadi

John M Khoury

Wayne Thomas Holcombe

Ramin Khoini-Poorfard

Sherry Xiaohong Wu

Francesco Barale

Yu Su

Pascal Blouin

Euisoo Yoo

Frederic Nicolas

David LeGoff

Yan Zhou

David S Trager

Guner Arslan

Krishna Pentakota

Steffen Skaug

Luigi Panseri

Chester Yu

Trenton John Grale

Jessica P Davis

Eric Mauger

Trent O Dudley

Paulo Pereira

John B Youngblood

J A Bolton

A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to amplify the delayed oscillating signal for transmission sufficient to produce interference, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

System and method of mitigating interference caused by coupling from power amplifier to voltage-controlled oscillator

In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.

Dual-band operation of a radio device

A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

Dual-mode power amplifier for wireless communication

A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.

Frequency selective attenuator for optimized radio frequency coexistence

A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.

Dynamically reconfigurable frequency selective attenuator for radio frequency receiver front end

In one embodiment, an apparatus includes: a digital baseband circuit to receive a digital baseband signal and output a first digital baseband signal and a second digital baseband signal, the second digital baseband signal comprising a scaled version of the first digital baseband signal; a first transmitter signal path coupled to the digital baseband circuit to process the first digital baseband signal and output a first radio frequency (RF) signal; a second transmitter signal path coupled to the digital baseband circuit to process the second digital baseband signal and output a second RF signal; a first power amplifier coupled to the first transmitter signal path to amplify the first RF signal and output an amplified first RF signal; and a second power amplifier coupled to the second transmitter signal path to amplify the second RF signal and output an amplified second RF signal.

Low power, efficient doherty power amplifier

An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.

System and method of duplicate circuit block swapping for noise reduction

An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.

A crystal driver integrated circuit with external oscillation signal amplitude control including an amplifier core, an input pin and an output pin, an adjustable capacitor, and a controller. The controller operates the amplifier core in any one of multiple operating modes including an oscillator mode and a bypass mode. During the bypass mode, the controller disables the amplifier core and adjusts the adjustable capacitor so that an amplitude of an oscillation signal received via the input pin from an external oscillator has a target amplitude. The external oscillation signal may be capacitively coupled for capacitive voltage division or directly coupled for impedance attenuation. An available voltage may be provided as a source voltage to the external oscillator via the output pin. An internal voltage regulator and/or switch may be included to re-provision the output pin to provide the source voltage during the bypass mode.

Crystal driver circuit with external oscillation signal amplitude control

An oscillation circuit including a crystal interface for coupling to a crystal, a crystal amplifier that drives the crystal to establish oscillation, a memory, a timing circuit, a level detector that provides an amplitude indication when an oscillation achieves a programmable threshold, and a controller. The controller applies one or more settings including gain and activates the crystal amplifier, measures the startup time, and calculates startup energy. The startup energy is based on a bias current of the crystal amplifier, remaining system current, and the startup time. The settings may include a gain setting of the crystal amplifier and one or more thresholds used by the threshold detector. The controller adjusts the settings for multiple startups, and determines optimal settings for minimizing the startup energy. The memory stores the optimal settings along with robust settings that may be used on a one-time basis in the event of startup failure.

Crystal oscillator adaptive startup energy minimization

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Austin, TX, United States of America

Vitor Pereira