Other

Idaho State University

Departmente of Informatics and Transportation (dimet)

University of Reggio Calabria Loc.

Vitit Kantabutra

Pasquale Corsonello

Stephania Perri

Bit blocks for an adder are provided which include a first bit stage that generates a first bit associated propagation characteristic (bapc). The bapc is independent of a carry input to the bit block from another bit block of the adder. Additional bit stages may be included in the bit block such as a second bit stage that, based on the first bapc, generates a second bapc that is also independent of the carry input to the bit block. The first and second bapc may be generated based on first and second operand bits input to the respective stages and a bapc that is generated by a less significant bit stage of the bit block and is independent of the carry input to the bit block. Adders including the bit blocks and methods for adding using the bit block as well as bit block size optimization methods are also provided.

Adders and adder bit blocks having an internal propagation characteristic independent of a carry input to the bit block and methods for using the same

A 64-bit precision digital circuit for computing the exponential function and a related 64-bit precision digital circuit for computing sine and cosine, each circuit comprising a master circuit and a slave circuit. The master circuit computes the remainders {tilde over (x)} for every &ldquo;logical&rdquo; iteration i using fast, low-precision circuit, thereby accumulating temporary errors. Only at the end of every 8 i's, which marks the end of a &ldquo;physical&rdquo; iteration, is a complete and fast correction to the accumulated errors performed. The slave circuit computes quantities called the y 's, which will eventually converge to the desired output.

Apparatus for computing exponential and trigonometric functions

An improved radix-4 CORDIC rotator iteration stage, using answer digits &lcub;&minus;3, &minus;1, 1, 3&rcub; instead of the conventional choices of &lcub;&minus;3, &minus;2, &minus;1, 0,1, 2, 3&rcub; or &lcub;&minus;2, &minus;1, 0, 1, 2&rcub;, thereby achieving constant magnitude amplification. The invention includes an answer digit decision module, which normally examines only a few digits of the remainder angle &thgr; , thereby saving time when compared to full-length comparison. Very rarely does the answer digit decision process involves examining close to all the digits of the remainder angle. When examining only a few digits of the remainder angle, the circuit takes only approximately 20% longer than a radix-2 CORDIC stage. The invented rotator stage is usable either as a pipeline stage or as a single-stage iterative circuit. For use in a pipeline, the invented stage is to be used only when only a few remainder angle bits need to be examined.

Efficient radix-4 CORDIC vector rotators and computers of sine and cosine functions

A 64-bit precision digital circuit for computing the exponential function and a related 64-bit precision digital circuit for computing sine and cosine, each circuit comprising a master circuit and a slave circuit. The master circuit computes the remainders x.sub.i for every 'logical' iteration i using fast, low-precision circuit, thereby accumulating temporary errors. Only at the end of every 8 i's, which marks the end of a 'physical' iteration, is a complete and fast correction to the accumulated errors performed. The slave circuit computes quantities called the y.sub.i 's, which will eventually converge to the desired output.

A carry-lookahead/carry-select binary adder includes a plurality of Manchester carry-lookahead cells arranged by length in monotonically increasing order at a first level and a carry-lookahead cell(s) at a second level connected to the first level cells. The cells generate corresponding groups of carry-propagate and carry-generate bits for respective portions of a first and a second binary operand to be summed. From each of the groups, a carry signal is derived for selecting the outputs of one of two parallel binary ripple adders. Based on the selection, the correct sum bits for respective portions of the first and a second binary operands are output. By arranging the first level cells in monotonically increasing order, the summation can occur quickly and each of the portions can be summed in a relatively uniform amount of time. In particular, the critical path delays associated with the summation of each of the portions are kept relatively uniform, based on a sum of the square of the length delay approximation. In the preferred embodiment, each of the binary ripple adders are replaced by a smaller-scale version of the hybrid adder itself. The hybrid adder can also be configured to add two 56-bit operands, which is ample for performing summation of the 52-bit mantissas of IEEE Standard-754 double-precision floating-point numbers. At this level of integration, a plurality of groups of Manchester carry-lookahead cells are implemented at the first level, and each group is arranged in monotonically increasing order.

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Pocatello, ID, United States of America

Vitit Kantabutra