Mosys, Inc.

Vithal Rao

Da-Guang Yu

Kameswara K Rao

Jawji Chen

Stephen Fung

J Eric Ruetz

Chee T Chua

A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.

Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process

A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

Two bits per cell non-volatile memory architecture

A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (I).

Growing community of inventors

San Jose, CA, United States of America

Vithal Rao