Motorola Corporation

Marvell International Limited

Cisco Technology, Inc.

Marvellworld Trade Ltd.

Marvell Israel (misl) Ltd.

Xelerated Newco Ab

Vitaly Sukonik

Sarig Livne

Jakob Carlström

Alex Miretsky

Mark Dunaevsky

Rafi Tamir

Gunnar Nordmark

Thomas Bodén

Rami Natan

Mattias Persson

Arie Ben-Ephraim

Rami Zemach

John H W Bettink

William Norman Eatherton

Moshe Voloshin

Avi Ginsberg

Einat Ophir

Amit Dor

Alexander Miretsky

Arie Kazachin

Bengt Werdin

Michael Brian Galles

Michael Laor

Amir Michaeli

Alexander Grobman

Neri Baron

Emil Marinov

Alexandre Saper

John H Bettink

The present invention relates to a data buffer memory () and method for storing data in a data communications network, and to a data buffer system () comprising such a data buffer memory. The data buffer memory comprising a data section (') comprising a number of memory pages (); and a package descriptor section (&#x2032;) comprising a 5 number of package descriptors (); wherein at least one queue () of packets is stored in the data section (&#x2032;) as an ordered set of packages, and wherein a package is an ordered set of packets.

Packet buffer comprising a data section and a data description section

Aspects of the disclosure provide a method for communicating queue information. The method includes determining a queue state for each one of a plurality of queues at least partially based on respective queue length, selecting a queue with a greatest difference between the queue state of the queue and a last reported queue state of the queue, and reporting the queue state of the selected queue to at least one node.

Method, network device, computer program and computer program product for communication queue state

A distributed network device and method for policing a flow of traffic in the chassis switch in communication networks. The distributed network device incudes a first processor configured to perform an egress processing operation on data packets received from a plurality second processor units in the distributed network switch, the data packets being destined for a receiving device coupled to the distributed network switch. Further, the distributed network device includes a metering unit associated with the first processor, the meting unit configured to meter a flow of the data packets to the receiving device and output a metering result. Also, the distributed network device includes a message generator configured to communicate to the plurality of second processors in the distributed network device a notification message indicative of the metering result.

Remote policing in a chassis switch

A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.

Network processor unit and a method for a network processor unit

There is provided a network device comprising a physical queue management processor configured to manage attributes of physical queues of data packets. The network device further comprises a scheduling processor which is configured to manage scheduling nodes that establish a scheduling hierarchy among the physical queues in a network, utilizing a bi-directional mapping of the physical queues to logical queues. The network device further comprises a traffic management processor which is configured to modify the bi-directional mapping mentioned above.

Dynamic reshuffling of traffic management scheduler hierarchy

In a method of processing packets in a network, a packet is received at an ingress port of a network device. A traffic class associated with the packet is determined. Based on the traffic class, it is determined whether the packet should transmitted without being enqueued by a traffic manager of the network device. When it is determined that that the packet should be transmitted without being enqueued by the traffic manager, the packet is sent to an egress port of the network device without enqueuing the packet by the traffic manager. When it is determined that the packet should not be transmitted without being enqueued in the network device, the packet is enqueued in a queue in the traffic manager of the network device. The packet sent to the egress port without being enqueued by the traffic manager is accounted for in the traffic manager.

Dummy queues and virtual queues in a network device

Aspects of the disclosure provide a method for network traffic scheduling. The method includes selecting, at a present node within a node hierarchy that multiplexes a plurality of input nodes to an output node, a winning node from a plurality of lower level nodes, obtaining first parameters provided from the winning node, the first parameters being in association with the winning node, determining second parameters in association with the present node at least partially based on the first parameters, and providing the second parameters in association with the present node to an upper level node in the node hierarchy for scheduling at the upper level node. To determine the second parameters in association with the present node, in an embodiment, the method includes using the first parameters to look up an entry in a lookup table that stores the second parameters in association with the first parameters.

Network traffic scheduler and associated method, computer program and computer program product

Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation.

Access scheduler

The disclosed embodiments relate to a system for controlling accesses to one or more memory devices. This system includes one or more write queues configured to store entries for write requests, wherein a given entry for a write request includes an address and write data to be written to the address. The system also includes a search mechanism configured to receive a read request which includes an address, and to search the one or more write queues for an entry with a matching address. If a matching address is found in an entry in a write queue, the search mechanism is configured to retrieve the write data from the entry and to cancel the associated write request, whereby the read request can be satisfied without accessing the one or more memory devices.

Access buffer

A method of and a network processor unit () for processing of packets in a network, the network processor () comprising: communication interface () configured to receive and transmit packets; at least one processing means () for processing packets or parts thereof; an embedded switch () configured to switch packets between the communication interface () and the processing means (); and wherein the embedded switch () is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means () for processing thereof, to receive the processed first part of the packet from the processing means (), and to transmit the processed first part of the packet.

Systems and methods are disclosed for implementing and using data structures comprised of a hierarchy of queues or linked list data structures. A queue or linked list typically comprises a distributor, a plurality of sub-queues or sub-linked lists, and a receiver. The distributor distributes a plurality of items to be added to the queue or linked list to the plurality of sub-queues or sub-linked lists in an order, and the receiver receives the items from these elements in the same order. Entries for the queues and/or linked lists may be stored in a common memory. Stages of selectors may be used to select a current queue or linked list and a particular sub-queue or linked list. The number of queues/linked lists and sub-queues/sub-linked lists is unbounded and can be sized according to the needs of the system, such as to overcome a memory access speed limitation.

Method and apparatus for a data structure comprising a hierarchy of queues or linked list data structures

Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques. In one implementation, a descriptor used in a prior DMA request is modified and then used in a second DMA request.

Methods and apparatus for processing packets including accessing one or more resources shared among processing engines

Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, a packet of multiple streams of packets is received. A subset of bytes of the packet are distributed to the next packet processor determined based on a distribution pattern. The subset of the packet is processed to generate a modified subset, which is gathered in turn based on the distribution pattern; and a modified packet including the modified subset is forwarded.

Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing engines

Growing community of inventors

Katzir, Israel

Vitaly Sukonik