Sun Microsystems, Inc.

Vit F Novak

Lawrence David Smith

An inductive compensation apparatus for smooth compensation of a transmission bus and methods of operating the same result in improved impedance of the transmission bus for transfer of data signals. The inductive compensation apparatus having an input and an output and a transmission bus with an effective impedance comprises a first capacitance connected to the input and a second capacitance connected to the output. A first bus compensator is connected between the input and the first capacitance to compensate the first capacitance and raise the impedance of the transmission bus. A second bus compensator is connected between the first capacitance and the second capacitance to compensate the first capacitance and the second capacitance and raise the impedance of the transmission bus. A third bus compensator is connected between the second capacitance and the output to compensate the second capacitance and raise the impedance of the transmission bus for improved data transfers on the transmission bus.

Method and apparatus for smooth inductive compensation of transmission

The present invention signals the power on, mated, and activity status of storage units in a console rack-mounted memory system. The status is signalled using parallel-coupled LEDs activated by logically combined signals provided by a logic circuit using signals available from SCA connector pins that connect the storage units to the console rack. The SCA connector provides MATED1 (pin 44), MATED2 (pin 74), and LED ACTIVE (pin 77) signals that are logically ANDed by the logic circuits. A logic circuit lights an associated parallel-coupled LED pair for a storage unit when LIT=MATED.multidot.ACTIVE LED, where MATED=0 denotes grounded pins 74 and (optionally) 44, and ACTIVE LED=0 denotes grounded pin 77, and LIT=l denotes lit LEDs. A steadily lit LED pair denotes that a storage unit is mated into the console rack and is inactive. An intermittent LED pair denotes that the storage unit is mated into the console rack and is presently active (and thus should not be removed). If no LEDs are lit on the console-rack, then it is known that operating power is not being provided to the memory system.

Power on, mated, and activity indicator for electronic devices including

Cold termination is provided at the bus output port of a last device coupled to a bus. Each device includes a termination integrated circuit ('TIC') that receives operating voltage from bus-provided V.sub.TERM potential. The TIC includes a series-coupled resistor-capacitor ('R-C') connected between V.sub.TERM and ground. The 'R-C' junction defines a SENSE node that is coupled to a groundable pin on the device bus output port and to a SENSE input node on the TIC. If a bus cable connector is attached to the device bus output port, attachment grounds the groundable pin, and thus the TIC SENSE node is '0', which disables TLC bus termination. But if no connector is attached, the groundable pin floats to a potential approximating V.sub.TERM, and is a logical '1', which enables TIC bus termination. Preferably an inverter is series-coupled between the TIC SENSE node and input SENSE node to accommodate a TIC that enables termination with a '0' input SENSE signal. A visual indicator coupled between V.sub.TERM and the inverter output illuminates when TIC bus termination is enabled. The present invention can cold terminate a wide-bus at a device, permitting the bus to propagate downstream as a narrow bus, and then cold terminate the narrow bus at the bus output port of a last device coupled to the bus.

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Los Altos, CA, United States of America

Vit F Novak