Texas Instruments Corporation

Viswanathan Sundararaman

Darvin R Edwards

Gregory Barton Hotchkiss

Michael F Chisholm

Reynaldo M Rincon

A conductive via pattern ( ) between the uppermost metal interconnect layer (M ) and next underlying metal interconnect layer (M ) in the bond pad areas strengthens the interlevel dielectric (ILD ) between metal layers (M and M ). The conductive via layer ( ) may, for example, comprise parallel rails ( ) or a grid of cross-hatch rails ( ). By spreading the stress concentration laterally, the conductive via layer ( ) inhibits micro-cracking from stress applied to the bond pad ( ).

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Dallas, TX, United States of America

Viswanathan Sundararaman