Skyworks Solutions, Inc.

Viswanathan Ramanathan

Hong Shen

Jiro Yota

Shiban Kishan Tiku

A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.

Wafer level chip scale filter packaging using semiconductor wafers with through wafer vias

According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.

Device packaging using a recyclable carrier substrate

An electronics package includes a semiconductor substrate having one or more passive devices formed thereon and a cavity defined in a first surface thereof. A piezoelectric substrate is bonded to the semiconductor substrate and has a radio frequency (RF) filter formed thereon. The RF filter is disposed within the cavity defined in the semiconductor substrate.

Gate structures for semiconductor devices include a silicon nitride layer, an electron beam evaporated tantalum nitride layer disposed on the silicon nitride layer, a first electron beam evaporated titanium layer disposed on the tantalum nitride layer, an electron beam evaporated gold layer deposited on the first titanium layer, and a second electron beam evaporated titanium layer deposited on the gold layer.

Gate structure with refractory metal barrier

Gate metallization structures and methods for semiconductor devices are disclosed, wherein a refractory metal barrier is implemented to provide performance improvements. Transistor devices are disclosed having a compound semiconductor substrate and an electron-beam evaporated gate structure including a layer of tantalum nitride (TaNx), a layer of titanium (Ti) and a layer of gold (Au).

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Thousand Oaks, CA, United States of America

Viswanathan Ramanathan