Agere Systems Inc.

Lsi Corporation

Nvidia Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Viswanath Annampedu

Pervez Mirza Aziz

Jeffrey Paul Grundvig

Xun Zhang

Amaresh Virupanagouda Malipatil

Vishnu Balan

Keith R Bloss

Venkatram Muddhasani

Roy S Neville

Vishal Narielwala

George Mathew

Hongwei Song

Yuan Xing Lee

Tianyang Ding

Pervez Mirzra Aziz

Adam Benjamin Healey

Peter John Windler

Jason D Byrne

Tomasz Prokop

Mark D Thornley

Fatih Sarigoz

Volodmyr Shvydun

Terence Karanink

Jeffery Grundvig

A receiver includes a partial response (PR) system that receives a received signal from a transmitter over a channel and equalize the received signal such that there is a controlled relationship between consecutive values of equalized received symbols and transmitted data transmitted by the transmitter. The receiver also includes a decision feed forward equalization (DFFE) system that receives partial response signals from the PR system and cancel at least one of pre-cursor intersymbol interference (ISI) or post-cursor ISI introduced by the channel.

Decision feed forward equalization for partial response equalized signal including pre-cursor cancelation

A receiver includes a decision feed forward equalization (DFFE) system that generates, based on a digital signal that includes at least one intersymbol interference (ISI) value introduced by a communication channel, a detected signal including a set of detected symbol values. The DFFE system cancels the at least one ISI value from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

A receiver includes a decision feed forward equalization (DFFE) system coupled to a partial response (PR) system. The partial response system generates, based on a digital signal that includes pre-cursor intersymbol interference (ISI) and post-cursor ISI introduced by a communication channel, a detected signal including a set of detected symbol values. The detected signal is equalized to a partial response. The DFFE system includes a PR inverter to generate a set of estimated transmitted symbol values based on the set of detected symbol values and DFFE circuitry to cancel the pre-cursor ISI and the post-cursor ISI from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

Decision feed forward equalization for intersymbol interference cancelation

A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defend number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.

Clock data recovery convergence in modulated partial response systems

A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

Clock data recovery convergence using signed timing injection

In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI.

Timing phase estimation for clock and data recovery

Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium.

Systems and methods for fly-height control using servo data

Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern.

Systems and methods for memory efficient repeatable run out processing

A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

Receiver with pipelined tap coefficients and shift control

In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.

Clock and data recovery architecture with adaptive digital phase skew

Improved flaw scan circuits are provided for repeatable run out data. RRO (repeatable run out) data is processed by counting a number of RRO data bits detected in a servo sector; and setting an RRO flaw flag if at least a specified number of RRO data bits is not detected in the server sector. The RRO flaw flag can also optionally be set by detecting an RRO address mark in the servo sector; counting a number of samples in the servo sector after the RRO address mark that do not satisfy a quality threshold; and setting the RRO flaw flag when the counted number of samples that do not satisfy the quality threshold exceeds a specified flaw threshold. If the RRO flaw flag is set, the RRO data can be discarded, and/or an error recovery mechanism can be implemented to obtain the RRO data.

Flaw scan circuit for repeatable run out (RRO) data

A multi-channel analog-to-digital (ADC) converter coupled to a clock-and-data-recovery loop that has a plurality of clock-recovery circuits, each configured to set the sampling phase for a respective one of the ADC channels in a manner that causes the different sampling phases to be appropriately time-aligned with one another for time-interleaved operation of the ADC channels. In an example embodiment, an individual clock-recovery circuit comprises a phase detector and a loop filter. Loop filters corresponding to different clock-recovery circuits may be coupled to one another by having shared circuit elements in their frequency-tracking paths and/or by being configured to receive timing gradients from more than one phase detector, including the phase detector of a selected one of the clock-recovery circuits.

Alignment of sampling phases in a multi-channel time-interleaved analog-to-digital converter

The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy.

System and method for determining channel loss in a dispersive communication channel at the Nyquist frequency

Various embodiments of the present invention provide systems and methods related to pattern detection. As an example, a system for sample selection is disclosed that includes a difference calculation circuit, a comparator circuit, and an output selector circuit. The difference calculation circuit is operable to calculate a first difference between a first value corresponding to a first digital sample and a second value corresponding to a second digital sample, and to calculate a second difference between a third value corresponding to a third digital sample and a fourth value corresponding to a fourth digital sample. The comparator circuit is operable to compare the first difference with the second difference to yield a comparison output. The output selector circuit is operable to select one of the second value and the fourth value as an output based at least upon the comparison output.

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Schnecksville, PA, United States of America

Viswanath Annampedu