Advanced Micro Devices Corporation

University of Michigan

Globalfoundries Inc.

Visvesh S Sathe

Samuel D Naffziger

Marios C Papaefthymiou

Srikanth Arekapudi

Jerry C Kao

Juang-Ying Chueh

Conrad H Ziesler

Stephen Victor Kosonocky

Kyle Viau

Charles Ouyang

Manivannan Bhoopathy

An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.

Constraining clock skew in a resonant clocked system

A resonant clock network includes an inductor coupled to the clock network through a plurality of switches. When the clock network enters resonant mode, the turn-on of the switches to couple the inductor to the clock network is staggered. The clock network may be formed of multiple regions, each with its own inductor and switches. The turn-on of switches of each region may be staggered with respect to the turn-on off the switches of the other regions as well as to the turn-on of switches within a region. In addition to staggering the turn-on of the switches when entering the resonant mode, the switches may be turned off in a staggered manner when exiting the resonant mode of operation.

Transitioning between resonant clocking mode and conventional clocking mode

A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.

Clock driver for frequency-scalable systems

A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.

Programmable clock driver

A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.

Controlling impedance of a switch using high impedance voltage sources to provide more efficient clocking

A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.

Sense-amplifier monotizer

A signal generator provides a plurality of oscillating signals, whereby each oscillating signal has a different peak voltage and has a predictable and consistent phase relationship with the other oscillating signals. The signal generator includes a plurality of stacked oscillators arranged between two reference voltages, such that each oscillator in the stack generates an oscillating signal having a different peak voltage. Each oscillator stage in a designated oscillator includes a transistor that is connected to a transistor of a corresponding stage in another oscillator. This arrangement of the oscillators provides for charge transfer between the corresponding stages to provide for similar voltage swings in each oscillating signal, as well as to provide for predictable phase relationship between the oscillating signals.

Oscillator device and methods thereof

Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Clock distribution network architecture with clock skew management

A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.

Interposer including voltage regulator and method therefor

Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.

Clock distribution network architecture for resonant-clocked systems

Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.

Clock distribution network architecture with resonant clock gating

A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.

Growing community of inventors

Fort Collins, CO, United States of America

Visvesh S Sathe