Advanced Micro Devices Corporation

Vishrut Vaibhav

Tad Robert Litwiller

Michael John Livesley

Todd Martin

Mangesh P Nijasure

Saad Arrabi

Techniques for performing rendering operations are disclosed herein. The techniques include providing indices and vertices to a culling shader; culling primitives and outputting primitives and indices that are not culled; and generating information for a fine binning pass based on the indices and primitives that are not culled.

Vertex index routing through culling shader for two level primitive batch binning

Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler. The techniques also include initiating a fine binning pass in which the sorted set of draw calls is processed through the world-space pipeline and the screen-space pipeline.

Vertex index routing for two level primitive batch binning

A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.

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Orlando, FL, United States of America

Vishrut Vaibhav