Intel Corporation

Vishram Shriram Pandit

Jayprakash Thakur

Ramaswamy Parthasarathy

Ajay Sharma

Satish Ramachandra

Stephen H Gunther

Manish Sharma

Eugene Gorbatov

Harish Krishnamurthy

Alexander Uan-Zo-Li

Arvind Sundaram

Michael Zelikson

Alexander Lyakhov

Sameer Shekhar

Philip R Lehwalder

Arik Gihon

Khondker Z Ahmed

Nimrod Angel

Patrick K Leung

Yagnesh Vinodrai Waghela

Punit Rathod

Nikita Ambasana

Neel Harkishin Bhatia

Rajiv Panigrahi

Vaibhavdeep Singh

Ravichandra Tungani Chikkabasavaiah

A wave launcher may include a printed circuit board (PCB) that includes a pin that receives a radio frequency (RF) signal. The wave launcher may include a cylinder configured to be electrically coupled to the pin and define an opening. The cylinder may receive the RF signal from the pin, form a transition from coplanar to Goubau line structure with a plate, and generate the surface wave. The wave launcher may include an insulator configured to be physically positioned within the opening and between the cylinder and a power line. The insulator may mechanically isolate the cylinder from the power line and permit the cylinder to launch the surface wave on the power line. The wave launcher may include the plate electrically coupled to a pad and may provide a reference for the pin and the cylinder. The pin and the cylinder may be physically positioned proximate the plate.

Surface wave launcher for high-speed data links over high-voltage power lines with loss compensation structure

In some implementations, an electronics system includes a voltage regulator circuit of a PDN configured to generate a power signal, a printed circuit board (PCB) comprising a power rail to deliver the power signal to a digital circuit generating an interfering signal. The PDN radiating the interfering signal or its harmonics impacting the functionality of destination antenna and circuits (such as Wi-Fi, Bluetooth, cellular, etc.). The system includes a filtering element configured to filter an interfering signal generated by the digital circuit. The filtering element includes a first set of low impedance (low-Z) segments and a second set of high impedance (high-Z) segments. The low-Z and high-Z segments are formed using a copper trace of the power rail and are serially connected to each other. The filtering element forms a low pass filter and filters out high frequency interfering signal going to the destination antenna and circuits by radiated means.

Mitigating PDN induced RF interference using a stepped impedance filter

A communication system communicates data elements on a conducting wire. In an embodiment, a sequence of data elements to be transmitted is electrically represented on a pair of terminals, and a transmission element located at a first portion of the conducting wire transmits the sequence in the form of a wave on a surface of the conducting wire. The transmission element includes a first conductor wrapped around the first portion of the conducting wire, a first insulator located between the first conductor and the first portion of the conducting wire, and a conductive structure disposed around the first conductor. The conductive structure has a narrow cross section at one end and extends outwardly to a broader cross section at the other end. A first terminal of the pair of terminals is electrically connected to the first conductor and the second terminal is electrically connected to the conductive structure.

Transmission of data over conducting wires

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Digital linear regulator clamping method and apparatus

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Bengaluru, India

Vishram Shriram Pandit