Micron Technology Incorporated

Vishnu Kumar Agarwal

Gurtej S Sandhu

Garo Jacques Derderian

Howard E Rhodes

Sam Yang

F Daniel Gealy

Scott J Deboer

Cem Basceri

Guy T Blalock

Garry Anthony Mercaldi

Dale G Fried

James S Foresi

Jean-Francois Viens

Scott G Meikle

Weimin Li

William Arthur Stanton

Mark R Visokay

Dinesh Chopra

Dan Gealy

Fred D Fishburn

Jeffrey A McKee

Rongsheng Yang

Kunal R Parekh

Randhir P S Thakur

Ravi T Iyer

Pai-Hung Pan

Martin Ceredig Roberts

Husam N Al-Shareef

Christopher W Hill

Gurtei Singh Sandhu

Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.

Polymer-based ferroelectric memory

A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.

Waveguide for thermo optic device

Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

The present technique relates to a device including an optical integrated circuit amplifier and another type of optical integrated circuit. The optical integrated circuit amplifiers and other optical integrated circuits are coupled together through optical paths. The optical integrated circuit amplifiers and other optical integrated circuits of the optical components are fabricated on the same substrate. The optical integrated circuit amplifiers and other optical integrated circuit amplifiers maybe fabricated on different levels of the same substrate.

Optical integrated circuit

An ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

Semiconductor device containing an ultra thin dielectric film or dielectric layer

In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly. The present invention also relates to a memory cell array comprising an array of wordlines and digitlines arranged to access respective memory cells within the array. Respective wordlines comprise a poly-metal stack formed over a semiconductor substrate in accordance with the present invention. Additionally, the present invention relates to a computer system comprising a memory cell array of the present invention.

Etch stop layer in poly-metal structures

A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly-metal stack. A semiconductor structure is also provided where an etch stop layer is present in the poly region of the poly-metal stack. The present invention also relates more broadly to a memory cell array and a computer system including the poly-metal stack of the present invention.

Self-aligned poly-metal structures

Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive layer of a semiconductor structure. A layer of an inhibiting substance may be used to inhibit a net flow of atoms so as to maintain conductivity between the metallization layer and the conductive layer of the semiconductor structure. Such layer of inhibiting substance acts even with the presence of point defects for a given temperature.

Structures and methods for improved capacitor cells in integrated circuits

Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.

Structurally-stabilized capacitors and method of making of same

The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received therebetween. The high K capacitor dielectric region has a high K substantially amorphous material layer and a high K substantially crystalline material layer. In one implementation, a capacitor forming method includes forming a first capacitor electrode layer over a substrate. A substantially amorphous first high K capacitor dielectric material layer is deposited over the first capacitor electrode layer. The substantially amorphous high K first capacitor dielectric material layer is converted to be substantially crystalline. After the converting, a substantially amorphous second high K capacitor dielectric material layer is deposited over the substantially crystalline first high K capacitor dielectric material layer. A second capacitor electrode layer is formed over the substantially amorphous second high K capacitor dielectric material layer.

Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric material

Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

Methods of enhancing capacitors in integrated circuits

A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

Growing community of inventors

Boise, ID, United States of America

Vishnu Kumar Agarwal