Nvidia Corporation

Vishnu Balan

Pervez Mirza Aziz

Mohammad Shafiul Mobin

Viswanath Annampedu

Rohit Rathi

Dai Dai

Sanjeev K Maheshwari

Lizhi Zhong

Arif Al Amin

Raanan Ivry

Olakanmi Oluwole

Akshay Shyam Pavagada Raghavendra

Pervez Mirzra Aziz

Gaurawa Kumar

Ky-Anh Tran

Sunil Rao Sudhakaran

Gautam Bhatia

Eric Tyson

Hitendra Dutt

Mohammed Mobin

Guo Hau Gau

Seunghyun Hwang

A receiver includes a partial response (PR) system that receives a received signal from a transmitter over a channel and equalize the received signal such that there is a controlled relationship between consecutive values of equalized received symbols and transmitted data transmitted by the transmitter. The receiver also includes a decision feed forward equalization (DFFE) system that receives partial response signals from the PR system and cancel at least one of pre-cursor intersymbol interference (ISI) or post-cursor ISI introduced by the channel.

Decision feed forward equalization for partial response equalized signal including pre-cursor cancelation

Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

Adapting forward error correction (FEC) or link parameters for improved post-FEC performance

A receiver includes a decision feed forward equalization (DFFE) system that generates, based on a digital signal that includes at least one intersymbol interference (ISI) value introduced by a communication channel, a detected signal including a set of detected symbol values. The DFFE system cancels the at least one ISI value from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several parameters. Each parameter controls at least a portion of the frequency response of the receiver. The optimal values for the parameters are determined by modifying an initial set of values for the parameters through one or more stochastic hill climbing operations until a performance metric associated with the receiver reaches a local optimum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the parameters.

Receiver and transmitter adaptation using stochastic gradient hill climbing with genetic mutation

An integrated circuit for a receiving link device includes a processing device to detect, using an equalizer of the receiving link device, that a receiver (RX) pre-cursor value is outside of a threshold value based on a target RX tap value. The processing device further generates, based on the detecting, a plurality of tap messages having a plurality of up or down commands to one of decrease or increase a corresponding transmitter (TX) pre-cursor value of a transmitting link device. The processing device further causes the plurality of tap messages to be provided to a local transmitter to be transmitted to the transmitting link device. The plurality of tap messages is to cause the transmitting link device to adjust the corresponding TX pre-cursor value.

Equalization adaptation schemes for high-speed links

A feed forward equalizer including a first set of filter taps having a first set of filter tap coefficients to be adapted and a second set of one or more filter taps having one or more filter tap coefficients to be constrained. The feed forward equalizer includes an adaptation component to determine a set of adapted filter tap coefficient values corresponding to the first set of filter tap coefficients and a constraint function component to determine a constrained filter tap coefficient value for the second set of the one or more filter taps having the one or more filter tap coefficients to be constrained using a constraint function based on at least a portion of the set of adapted filter tap coefficient values. The feed forward equalizer generates, based at least in part on the constrained filter tap coefficient value, an equalized signal including a set of estimated symbol values.

Feed forward filter equalizer adaptation using a constrained filter tap coefficient value

A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

A receiver includes a decision feed forward equalization (DFFE) system coupled to a partial response (PR) system. The partial response system generates, based on a digital signal that includes pre-cursor intersymbol interference (ISI) and post-cursor ISI introduced by a communication channel, a detected signal including a set of detected symbol values. The detected signal is equalized to a partial response. The DFFE system includes a PR inverter to generate a set of estimated transmitted symbol values based on the set of detected symbol values and DFFE circuitry to cancel the pre-cursor ISI and the post-cursor ISI from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

Decision feed forward equalization for intersymbol interference cancelation

A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defend number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.

Clock data recovery convergence in modulated partial response systems

A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several frequency response parameters. Each frequency response parameter controls at least a portion of the frequency response of the receiver. The optimal values for the frequency response parameters are determined by modifying an initial set of values for the frequency response parameters through one or more of stochastic hill climbing operations until a performance metric associated with the receiver reaches a local maximum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the frequency response parameters.

A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

Clock data recovery convergence using signed timing injection

This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion

A clock data recovery (CDR) mechanism qualifies symbols received from the data detector prior to using those symbols to compute a timing gradient. The disclosed CDR mechanism analyzes one or more recently received symbols to determine whether the current symbol should be used in computing the time gradient. When configured with a Mueller-Muller phase detector, the timing gradient for the received signal is set to zero if the current symbol is a &#x2212;2 or a +2 and the previous symbol is non-zero. Otherwise, the Mueller-Muller timing gradient is evaluated in the traditional manner. When configured with a minimum mean-squared error phase detector, the timing gradient for the received signal is set to zero if the previous symbol is non-zero. Otherwise, the minimum mean-squared error timing gradient is evaluated in the traditional manner.

Clock data recovery mechanism

Receiver adaptation using stochastic gradient hill climbing with genetic mutation

This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

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Saratoga, CA, United States of America

Vishnu Balan