Freescale Semiconductor,inc.

Nxp Usa, Inc.

Applied Novel Devices, Inc.

Other

University of Florida Research Foundation, Incorporated

Freescale Semiconductors Inc.

Vishal P Trivedi

Jay Paul John

Leo Mathew

James Albert Kirchgessner

Kun-Hin To

Rajesh A Rao

Da Zhang

Gregory S Spencer

Daniel Fine

David Gareth Morgan

Pamela J Welch

Wen Ling M Huang

Chun-Li Liu

Michael Alan Sadd

Voon-Yew Thean

Brian A Winstead

Tab Allen Stephens

Michael D Turner

Olin L Hartin

Venkat Kolagunta

Dharmesh Jawarani

Laegu Kang

Hernan A Rueda

Jerry G Fossum

David C Sing

Narayanan C Ramani

John J Hackenberg

Daniel G Tekleab

Hernan A Reuda

A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first side of the substrate.

Structures and methods of fabricating electronic devices using separation and charge depletion techniques

A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.

Semiconductor device structure with non planar slide wall

High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher f.

Semiconductor devices with recessed base electrode

Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes an active-circuit arrangement that facilitates generation of an oscillating signal, and a resonator arrangement capacitively coupled to the active-circuit arrangement to influence an oscillation frequency of the oscillating signal based on a difference between a first control voltage and a second control voltage.

Voltage-controlled oscillators and related systems

A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.

Electronic device including interconnects with a cavity therebetween and a process of forming the same

Apparatus are provided for voltage-controlled oscillators (VCOs) and related systems. An exemplary VCO includes an active-circuit arrangement employing cross-coupled amplifying elements that facilitate generation of an oscillating signal, plus a resonator arrangement capacitively coupled via resonator terminals to primary terminals of the active-circuit arrangement, to influence an oscillation frequency of the oscillating signal based on a difference between control voltages applied to first and second control terminals of the resonator arrangement. When employing bipolar amplifying elements their control terminals are cross-coupled to the opposing resonator terminals. VCO output may be taken from the primary terminals or from the resonator terminals.

A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor.

Methods for forming transistors

A hybrid transistor () has a substrate () with a first (e.g., P type) well region () and a second (e.g., N type) well region () with an NP or PN junction () therebetween. A MOS portion (-) of the hybrid transistor () has an (e.g., N type) source region () in the first well region () and a gate conductor () overlying and insulated from the well regions () that extends laterally at least to the junction (). A drain or anode (D/A) portion (-) in the second well region () collects currentfrom the source region (), and includes a bipolar transistor () having an (e.g., N+) emitter region (), a (e.g., P type) base region () and a (e.g., N type) collector region () laterally separated from the junction (). Different LDMOS-like or IGBT-like properties are obtained depending on whether the currentis extracted from the hybrid transistor () via the bipolar transistor () base () or emitter () or both. The bipolar transistor () is desirably a vertical hetero-junction transistor.

Hybrid transistor

High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, intrinsic base and collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing R. Smaller Rprovides transistors with higher f.

Bipolar transistor and method with recessed base electrode

Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes a first variable capacitance element, a second variable capacitance element coupled between the first control voltage node and the third node, and an inductive element coupled between the variable capacitance elements to provide an inductance between the variable capacitance elements at an oscillation frequency of an oscillating signal at an output node. The first variable capacitance element is coupled between a first control voltage node and the output node, the second variable capacitance element is coupled to the first control voltage node, and a second inductive element is coupled between the second variable capacitance element and a second control voltage node.

Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Two-transistor floating-body dynamic memory cell

A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Growing community of inventors

Chandler, AZ, United States of America

Vishal P Trivedi