Cadence Design Systems, Inc.

Vishal Karda

Naresh Kumar

Sushobhit Singh

Ankur Gulati

Shashank Prasad

Beenish

The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.

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Greater Noida, India

Vishal Karda