Freescale Semiconductor,inc.

Vishal Gupta

Puneet Dodeja

Manish Kumar Mittal

Sarvesh Verma

Hans Raj Singh

A system for re-ordering a scan chain of an electronic circuit design using an electronic design automation (EDA) tool includes a processor and a memory in communication with the processor. The scan chain includes a plurality of scan cells. All connections of the scan chain are disconnected. An output port of a first scan cell is connected to input ports of other scan cells to form a first set of scan cell combinations. A first scan cell combination is selected from the first set of scan cell combinations based on weighted averages of ordering parameters of each of the first set of scan cell combinations. The process is repeated to re-order the scan chain.

System and method for scan chain re-ordering

An integrated circuit (IC) design includes configurable circuits arranged in a mesh structure to facilitate routing of signals between different platforms or logic blocks within the design. Each configurable circuit has a semiconductor element with input and output terminals in a first semiconductor layer, input/output (I/O) ports corresponding to directions of the mesh structure in a second semiconductor layer, configurable input vias to allow a signal traveling in a first direction to be received, and configurable output vias that allow an output signal to be output from the configurable circuit in a second direction.

Configurable circuit and mesh structure for integrated circuit

A method for reordering scan chain segments of scan chains in an electronic circuit design includes identifying congestion areas on a congestion map. A routing preference for each congestion area is determined. Scan cells associated with each congestion area are formed into the scan chain segments and then the scan chain segments are re-ordered based on the routing preference of the corresponding congestion area.

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Noida, India

Vishal Gupta