Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Vsli Technology, Inc.

Vishal Anand

Desi Rhoden

In an example embodiment, an apparatus providing communication in a computer system, comprises, a plurality of modules each having a master port and a slave port A secondary bus is shared between the plurality of modules for transmitting data and address information between a master port and a slave port of two modules. A bridge circuit coupled to the plurality of modules and the secondary bus, individually grants modules of the plurality of modules, access to the secondary bus. The bridge circuit establishes point-to-point communication paths between a master port and a slave port of two modules of the plurality of modules, for communicating handshake signals between them, and controls address and data phases between modules; two address phases can be outstanding simultaneously. The bridge circuit forwards address and data phases from one module to another module of the plurality of modules; the plurality of modules only interface with the bridge circuit.

High performance internal bus for promoting design reuse in north bridge chips

An optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks. A system in accordance with the present invention communicatively couples the internal components (e.g., CPU, memory, etc.) and peripheral devices (e.g., display, keyboard, etc.) of a computer system by dividing the components into two logical subdivisions. One subdivision includes the memory and CPU(s) of the computer system while the other subdivision includes the remaining components. In accordance with the present invention, each subdivision of components is interconnected to the other components of its subdivision by a bus scheme. Both subdivision bus schemes are interconnected by circuitry referred to as a bridge, which enables them to intercommunicate. As such, the components connected to the separate subdivision bus schemes are able to intercommunicate. By implementing the intercommunication of computer system components in this manner, a substantial part of the interconnection circuitry of the computer system is typically reusable when significant modifications are subsequently implemented within future related computer systems. Furthermore, this system in accordance with the present invention does not become overly complex and/or excessively large when significant modifications are later implemented.

Optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks

An interface and process for re-ordering data transactions between a master device and a target device. The present invention applies to target devices that interface to master devices such that both masters and slaves are capable of handling the re-ordering of outstanding requests. In such an interface where data transactions can be in any order, certain events may occur that force the reordering to be limited to either before or after the event. These events, also referred to as synchronizing events herein, require that transactions sampled before the event must be completed before transactions sampled after the event are completed. The present invention is capable of handling such synchronizing events while maximizing reordering to gain maximum performance benefits.

Interface and process for handling out-of-order data transactions and synchronizing events in a split-bus system

An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1) log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue. Further, each output address selection circuit includes an output address list pointing to occupied storage locations in the main queue, and, the output address lists are updated each time an access request is stored in, or read out from, the main queue. The present embodiment further comprises a control circuit for determining a request type of each incoming request, and for transmitting addresses from the input address list to the output address lists each time an access request is stored in the main queue.

Single address queue for handling multiple priority requests

A method of and a system for allowing cacheable system memory to be accessed in a non-cacheable manner. In one embodiment of the present invention, a computer system is tricked during POST (Power-On Self-Test) to reserve a first region in a non-cacheable address space for a virtual peripheral device. The computer system is then tricked during operating system startup to reserve a second region in a cacheable address space. In the present embodiment, the first region is then mapped to the second region such that accesses to the first region is automatically forwarded to the second region. As a result, objectives of the present invention are achieved as cacheable memory may be accessed via accessing non-cacheable memory of the computer system.

Method of and system for allowing a computer system to access cacheable

An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1)log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue. Further, each output address selection circuit includes an output address list pointing to occupied storage locations in the main queue, and, the output address lists are updated each time an access request is stored in, or read out from, the main queue. The present embodiment further comprises a control circuit for determining a request type of each incoming request, and for transmitting addresses from the input address list to the output address lists each time an access request is stored in the main queue.

A centrally controlled interface scheme for promoting design reusable circuit blocks. A system in accordance with the present invention enables existing circuit blocks of a computer system to be connected in a wide variety of shared bus standards while their internal circuitry remains unchanged. Specifically, within an embodiment of the present invention, the sharing of signals over a shared bus scheme is exclusively controlled by external bus control circuits which are controlled by an external control unit. As such, the circuit blocks are designed to operate as if they have dedicated (e.g., point-to-point) lines to the other circuit blocks with which they communicate. By implementing the circuit blocks and external control of the shared signals in this fashion, the bus interconnection scheme of the circuit blocks can be changed to fit desired performance levels or expected traffic levels, while the circuit blocks themselves remain unchanged. Consequently, little or no time is required redesigning existing circuit blocks when bus modifications are implemented within future computer systems which still utilize the existing circuit blocks. Instead, only modifications are required to the external circuitry which controls the shared signals of the circuit blocks, which is substantially easier than redesigning existing circuit blocks.

Centrally controlled interface scheme for promoting design reusable

A method and system for latching an address for accessing a synchronous static random access memory (SRAM). A first address status signal of the SRAM is driven active, triggering an SRAM to latch the address on an address bus coupled therewith. A second address status signal is received when a valid address is placed on the address bus. In response, the first address status signal is driven inactive. This forces the last address latched by the SRAM to be the one indicated by the second address status signal. Then, a determination is made as to whether SRAM access is required based on the address placed on the bus. SRAM access may not be required if the current cycle is either non-cacheable or a miss in the SRAM. When SRAM access is not required, the first address status signal is driven active. In the alternative, when SRAM access is required, the first address status signal is maintained inactive. The first address status signal is maintained inactive until the SRAM is ready to accept a second address.

Growing community of inventors

Fremont, CA, United States of America

Vishal Anand