Codeon Corporation

Other

Nvidia Corporation

Vishal Agarwal

Larry A Hess

William K Burns

Amit D Sanghani

Milind Bhaiyyasaheb Sonawane

Anubhav Sinha

Satya Puvvada

Williams K Burns

A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

Global low power capture scheme for cores

An optical waveguide device including an electro-optical crystal substrate having a top surface and a bottom surface; an optical waveguide path formed within a surface of the electro-optical crystal substrate; at least one electrode positioned above the optical waveguide path for applying an electric field to the optical waveguide path; and a silicon titanium oxynitride layer and a connecting layer for interconnecting the silicon titanium oxynitride layer to another surface of the electro-optical crystal substrate that is opposite to the surface in which the optical waveguide path is formed.

Buffer layer structures for stabilization of a lithium niobate device

Growing community of inventors

Sunnyvale, CA, United States of America

Vishal Agarwal