Oracle International Corporation

Vishak Chandrasekhar

Jurgen M Schulz

Wayne F Seltzer

Brian McGee

Yu-Cheng Chiu

Yu-cheng Chiu

Integrated circuit devices, methods, and other embodiments associated with power throttling with temperature sensing and activity feedback are described. In one embodiment, an integrated circuit device includes temperature sensing logic, activity sensing logic, comparison logic, and signal logic. The temperature sensing logic is configured to output a temperature signal indicative of a temperature of a selected region of the device. The activity sensing logic is configured to output an activity signal indicative of a level of activity of a selected device function. The mode selection logic is configured to select the temperature signal or the activity signal. The comparison logic is configured to compare the selected signal to a series of threshold levels and output a comparison result. The signal logic is configured to generate a throttle signal based on the comparison result. The throttle signal is used to control a frequency of operation of a selected device component.

Power throttle mechanism with temperature sensing and activity feedback

A system, comprising: a first local controller (LC) having a first position in a ring network and comprising a first LC cycle counter; a second LC having a second position in the ring network and comprising a second LC cycle counter; and a central controller (CC) connected to the ring network and comprising: a data structure linking the first LC to the first position and linking the second LC to the second position; and a CC cycle counter.

Transfer of information within an ASIC using a slotted ring based protocol

The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.

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San Jose, CA, United States of America

Vishak Chandrasekhar