Texas Instruments Corporation

Vish Visvanathan

Vinod J Menezes

Sharad Kumar Gupta

Dharin Nayeshbhai Shah

Shahid Ali

Aman A Kokrady

Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.

Error prediction in logic and memory devices

A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

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Chennai, India

Vish Visvanathan