Nvidia Corporation

Meta Platforms, Inc.

Visalakshi Vaduganathan

Harikrishna Madadi Reddy

Prahlad Venkatapuram

Deepa Palamadai Sundar

Atul Garg

Wei Sun

Ignatius B Tjandrasuwita

Lefan Zhong

Leonardo Vainsencher

Manindra Parhy

Ram Prabhakar

Shu-Jen Fang

Xing Cindy Chen

Krishna Kishor Noru

Karunakar Rachamreddy

Nitin Jadon

Techniques to optimize memory reads when computing a video quality metric are disclosed. In some embodiments, an application-specific integrated circuit for computing video quality metrics includes a set of caches configured to store neighbor pixel data for edge width searches of pixels comprising a frame of a video being analyzed for a video quality metric and a kernel configured to receive corresponding neighbor pixel data for pixels comprising a current processing block of the frame from a subset of the set of caches and simultaneously perform edge width searches for pixels comprising the current processing block to determine corresponding pixel edge width values used for computing the video quality metric.

Optimizing memory reads when computing video quality metrics

A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.

Scalable accelerator architecture for computing video quality metrics

Techniques for synchronizing error concealment during video decoding include determining a decoding error. A recovery point within a current frame is determined for each decoding error. The determined recovery point may be the start of the next good slice of a frame after the current frame containing the error. The number of macroblock to be concealed is also determined. The determined number of macroblocks from the recovery point may then be concealed in hardware or software. The techniques for concealing errors may also include determining available macroblocks for use in concealing the error. The techniques for concealing errors may further include selecting a given concealment mode.

Video decoding error concealment techniques

The present invention facilitates efficient and effective detection of pixel alteration. The number and configuration of pixels in a block partition can be flexibly changed. The filter inputs in the multi-protocol filter can be flexibly changed to meet the deblocking requirement in the target video compression standard. In one embodiment, the deblock engine includes an input interface, a neighbor buffer, a current data buffer; and a multi-protocol filter. The input interface receives reconstructed data. The neighbor buffer temporarily stores neighbor information. The current data buffer receives the reconstructed data and the neighbor information. The multi-protocol filter filters information selected from the reconstructed data and neighbor information.

Multi-protocol deblock engine core system and method

A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

Dynamic packet size control for MPEG-4 data partition mode

The present invention facilitates efficient and effective detection of pixel alteration. In one embodiment a pixel alteration analysis system includes a difference summing multiple engine component and a control component. The difference summing multiple engine component determines the sum of differences between pixel values in a plurality of pixels. The control component determines an indication of motion based upon said relationship of said pixels in said plurality of pixels. In one exemplary implementation, the difference in values corresponds to a relationship between values of pixels in a block of pixels at different frames. The number and configuration of pixels in a block partition can be flexibly changed.

Adaptive multiple engine image motion detection system and method

Growing community of inventors

Fremont, CA, United States of America

Visalakshi Vaduganathan