Siemens Aktiengesellschaft

International Business Machines Corporation

Kabushiki Kaisha Toshiba

Applied Materials, Inc.

Siemens Components, Inc.

Virinder Grewal

Bruno Spuler

Ajay Kumar

Munir D Naeem

Masaki Narita

Stuart M Burns

Werner Reindl

Wai-Fan Yau

Tokuhisa Ohiwa

Nancy Anne Greco

Anisul Haque Khan

Dragan Valentin Podlesnik

Stephan Wege

Ernest N Levine

Peter D Hoh

Waldemar Walter Kocon

Sharma V Pamarthy

Rainer F Schnabel

Bernhard Poschenrieder

Bernd M Vollmer

Chi-Hua Yang

Klaus Feldner

Rosemary Christie

Axel Henke

Steve Greco

Walter W Kocon

Guadalupe Wiltshire

A method and apparatus for process integration in manufacture of a ask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.

Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the same

A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

Method for etching high-aspect-ratio features

An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying device layer and separated therefrom by insulating material at a bottom of the trench. The method also includes, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Further, the method includes, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying device layer to form a via.

Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide

A method for forming integrated circuit conductors. The method includes the steps of placing in a reactive ion etching chamber a semiconductor body having disposed over a surface thereof: a metalization layer comprising an aluminum layer disposed between a pair of barrier metal layers; and, a photoresist layer disposed on a selected portion of a surface of an upper one of the pair of barrier layers. Radio frequency energy is inductively coupled into the chamber while silicon tetrachloride and chlorine are introduced into the chamber at rates selected to etch portions of the metalization layer exposed by the photoresist with aluminum having substantially vertical sidewalls. The silicon tetrachloride is introduced into the chamber at a rate in the range of 4 to 8 sccm. The rate of the chlorine is in the range of 50 sccm to 150 sccm. The chamber is at a pressure of about 12 milliTorr during the etching of the metalization layer. The chamber operates with an RF power of about 125 watts while the semiconductor is disposed on a platform in the chamber having an RF bias power level of about 250 watts during the etching.

Method for patterning integrated circuit conductors

RIE of metallization is achieved at low power and low pressure using Cl.sub.2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl.sub.2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl.sub.2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl.sub.2 and HCl and an inert gas, such as N.sub.2 are controlled in a manner such that a very thin side wall layer (10-100 .ANG.) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching. The side wall layer improves the isotropic nature of the etch such that submicron metallization lines with defect free side walls are formed. Hydrogen (H.sub.2) can be added to the plasma and will act to reduce corrosion.

Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal

Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl.sub.2 at a volumetric flowrate ratio of HCl:Cl.sub.2 within the range of 3:1 to 5:1.

Polycide etching with HCL and chlorine

A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.

Methods for metal etching with reduced sidewall build up during

A method of forming a self-aligned overlapping bitline contact, includes steps of first depositing a sacrificial polysilicon on a spacer dielectric film, and thereafter patterning the polysilicon. The polysilicon film is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide on the polysilicon, and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon is etched and the spacer dielectric film is etched to form a self-aligned bitline contact.

Formation of self-aligned overlapping bitline contacts with sacrificial

A method for producing contact holes having sloped walls in intermediate oxide layers through combination of isotropic and anisotropic etching steps which are carried out by means of dry etching in a fluorine-containing plasma. The first etching step is an isotropic etching using an etching gas mixture in which the free fluorine atoms for the isotropic etching step are partially replaced by free CF.sub.3 radicals and ions for the anisotropic etching step. The last etching step is carried out anisotropically. Simultaneously, the electrode spacing in the reactor is reduced during the etching process. Sidewall angles between 60.degree. and 90.degree. can be reproduced with the method of the present invention. The method is particularly useful for the manufacture of large scale integrated semiconductor circuits.

Method for generating contact holes with beveled sidewalls in

A mirror structure which is provided on a polished metallic surface characterized by an adhesive layer disposed directly on the surface, an amorphous intermediate layer disposed on the adhesive layer, a reflective layer disposed on the amorphous intermediate layer and a protective layer covering the reflective layer. The mirror structure is particularly useful for a highly adhesive and corrosion-proof laser mirror which has good reflection properties and is used in a laser flatbed scanner.

Mirror structure

A method for manufacturing solderable, temperable thin film tracks which do not contain precious metal on an electrically non-conductive substrate serving as a carrier employs the steps of applying an adhesive or resistance layer to the substrate, which serves as an intermediate layer, applying a conductive layer over the intermediate layer, and applying a protective anti-corrosion layer over the conductive layer. The protective layer may consist of aluminum or an aluminum alloy, or may be comprised of a combination of a layer of aluminum and a layer of chrome. An aluminum layer may also be applied between the intermediate layer and the conductive layer.

Growing community of inventors

Ebersberg, Germany

Virinder Grewal