Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Centre National De La Recherche Scientifique

Université Grenoble Alpes

Virginie Loup

Pascal Besson

Shay Reboh

Jean-Michel Hartmann

Thierry Baron

Laurent J Vallier

Mickaël Martin

Pierre-Edouard Raynal

A method for manufacturing a semiconductor-on-insulator substrate by BESOI comprising the following steps: a) provide a structure comprising a first substrate, a first stopping layer made of SiGe having an atomic percentage of Ge lower than or equal to 30%, an intermediate layer, a second stopping layer made of SiGe having a thickness smaller than the thickness of the first stopping layer and an atomic percentage of Ge higher than or equal to 20%, optionally an active area formed by a layer made of silicon or by a stack of active layers made of Si and SiGe, a dielectric layer, a second substrate, b) thin and then etch the first substrate made of silicon, from the first main face up to the second main face, c) successively remove the first stopping layer, the intermediate layer, and optionally the second stopping layer to obtain a SOI or SiGeOI substrate.

Method for manufacturing a SOI or SiGeOI type semiconductor-on-insulator substrate by BESOI and structure for manufacturing such a substrate

A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Process for the hetero-integration of a semiconductor material of interest on a silicon substrate

A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

Method for fabricating a monocrystalline structure

A method for performing selective etching of a semiconductor material in solution having the following successive steps: a) providing a substrate having a layer of amorphous semiconductor material to be etched and a layer of crystalline semiconductor material; b) oxidizing the surfaces of the layers of amorphous semiconductor material and of crystalline semiconductor material so as to form a first protective layer at the surface of the amorphous semiconductor material and a second protective layer at the surface of the crystalline semiconductor material; c) etching the first protective layer and the layer of amorphous semiconductor material with an alkaline etching solution, the etch rate vof the first protective layer being higher than the etch rate vof the second protective layer.

Growing community of inventors

Saint-Egrève, France

Virginie Loup