International Business Machines Corporation

Virgil D Wyatt

Nandor G Thoma

Wayne R Kraft

Moises Cases

William L Stahl, Jr

William E Tutt

An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines. The buffer stages for each programmable logic array are responsive to the strobe signal for its programmable logic array for discharging during the second time interval those bus lines for which its programmable logic array output lines are at a particular binary value.

Integrated circuit mechanism for coupling multiple programmable logic

A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus. The signal transfer mechanism further includes processor control circuitry coupled to the signal source and signal destination circuitry for enabling the signal source circuitry to put a plural-bit data signal onto the data bus during a first processor control cycle and for enabling the signal destination circuitry to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.

Large scale integration data processor signal transfer mechanism

This invention relates to controls for a control store made of plural modules which operate in an overlapped continuous manner, wherein the modules are cycled in a fixed sequence. This invention particularly relates to a novel next address generation and handling means for a control store using time interleaved modules.

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Lighthouse Point, FL, United States of America

Virgil D Wyatt