Intel Corporation

Virendra Vikramsinh Adsure

Chia-Hung Sophia Kuo

Barnes Cooper

Jianfang Olena Zhu

Deepak Samuel Kirubakaran

Jianwei Dai

Deepak Gandiga Shivakumar

Ivan Chen

Martin Guy Dixon

Kristoffer Fleming

Robert J Royer, Jr

Michael D Rosenzweig

Jaya L Jeyaseelan

Nadav Bonen

Toby Opferman

Mark J Gallina

Duncan Glendinning

Yifan Li

Jin Yan

Adam J Norman

Vijay Bahirji

Amir Ali Radjai

Taeyoung Kim

Nivedha Krishnakumar

Kai P Wang

An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.

Methods and apparatus to adapt memory channel usage on a per-user basis

Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

Methods, systems, and apparatus to reconfigure a computer

Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.

Techniques to reduce memory power consumption during a system idle state

A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

Memory power management method and apparatus

Growing community of inventors

Folsom, CA, United States of America

Virendra Vikramsinh Adsure