Qualcomm Incorporated

Viraphol Chaiyakul

Inyup Kang

Chihtung Chen

Tauseef Kazi

Lukai Cai

Haobo Yu

Mahesh Sridharan

Chih-tung Chen

An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.

Concurrent multiple-dimension word-addressable memory architecture

An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.

Systems and methods for improving digital system simulation speed by clock phase gating

An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.

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Viraphol Chaiyakul